diff --git a/source/abstraction/gw-start.s b/source/abstraction/gw-start.s
index 18baab8..691c0e7 100644
--- a/source/abstraction/gw-start.s
+++ b/source/abstraction/gw-start.s
@@ -6,36 +6,36 @@
 .arm
 
 _vectors:
-	ldr pc, =InfiniteLoop
-	.pool
-	ldr pc, =InfiniteLoop
-	.pool
-	ldr pc, =InfiniteLoop
-	.pool
-	ldr pc, =InfiniteLoop
-	.pool
-	ldr pc, =InfiniteLoop
-	.pool
-	ldr pc, =InfiniteLoop
-	.pool
+    ldr pc, =InfiniteLoop
+    .pool
+    ldr pc, =InfiniteLoop
+    .pool
+    ldr pc, =InfiniteLoop
+    .pool
+    ldr pc, =InfiniteLoop
+    .pool
+    ldr pc, =InfiniteLoop
+    .pool
+    ldr pc, =InfiniteLoop
+    .pool
 
 _start:
-	ldr sp,=0x22140000
+    ldr sp,=0x22140000
 
-	@@wait for the arm11 kernel threads to be ready
-	ldr r1, =0x10000
-	waitLoop9:
-		sub r1, #1
+    @@wait for the arm11 kernel threads to be ready
+    ldr r1, =0x10000
+    waitLoop9:
+        sub r1, #1
 
-		cmp r1, #0
-		bgt waitLoop9
+        cmp r1, #0
+        bgt waitLoop9
 
-	ldr r1, =0x10000
-	waitLoop92:
-		sub r1, #1
+    ldr r1, =0x10000
+    waitLoop92:
+        sub r1, #1
 
-		cmp r1, #0
-		bgt waitLoop92
+        cmp r1, #0
+        bgt waitLoop92
 
     @ Enable caches
     mrc p15, 0, r4, c1, c0, 0  @ read control register
@@ -45,12 +45,12 @@ _start:
     orr r4, r4, #(1<<0)        @ - mpu enable
     mcr p15, 0, r4, c1, c0, 0  @ write control register
     
-	ldr sp,=0x22160000
-	ldr	r3, =main
-	blx r3
+    ldr sp,=0x22160000
+    ldr    r3, =main
+    blx r3
 .pool
 
 InfiniteLoop:
-	b InfiniteLoop
+    b InfiniteLoop
 
 #endif // EXEC_GATEWAY