From 42fafc5d9b9a37fe270535373090918c072a1405 Mon Sep 17 00:00:00 2001
From: d0k3 <tore.anon@gmail.com>
Date: Fri, 10 Jun 2016 16:59:12 +0200
Subject: [PATCH] Cleaned up start.s files

---
 source/abstraction/a9-start.s | 10 ++++------
 source/abstraction/gw-start.s | 10 ++++------
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/source/abstraction/a9-start.s b/source/abstraction/a9-start.s
index 6cca4cf..6a7a550 100644
--- a/source/abstraction/a9-start.s
+++ b/source/abstraction/a9-start.s
@@ -28,9 +28,7 @@ _start:
     ldr r5, =0x20000037	@ 20000000 256M | fcram (O3DS / N3DS)
     ldr r6, =0x1FF00027	@ 1FF00000 1M   | dsp / axi wram
     ldr r7, =0x1800002D	@ 18000000 8M   | vram (+ 2MB)
-    mov r10, #0x25
-    mov r11, #0x25
-    mov r12, #0x25
+    mov r8, #0x2D
     mcr p15, 0, r0, c6, c0, 0
     mcr p15, 0, r1, c6, c1, 0
     mcr p15, 0, r2, c6, c2, 0
@@ -39,9 +37,9 @@ _start:
     mcr p15, 0, r5, c6, c5, 0
     mcr p15, 0, r6, c6, c6, 0
     mcr p15, 0, r7, c6, c7, 0
-    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
+    mcr p15, 0, r8, c3, c0, 0	@ Write bufferable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 0	@ Data cacheable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 1	@ Inst cacheable 0, 2, 5
 
     @ Enable dctm
     ldr r1, =0x3000800A        @ set dtcm
diff --git a/source/abstraction/gw-start.s b/source/abstraction/gw-start.s
index 5ddd33a..f3865b6 100644
--- a/source/abstraction/gw-start.s
+++ b/source/abstraction/gw-start.s
@@ -58,9 +58,7 @@ _start:
     ldr r5, =0x20000037	@ 20000000 256M | fcram (O3DS / N3DS)
     ldr r6, =0x1FF00027	@ 1FF00000 1M   | dsp / axi wram
     ldr r7, =0x1800002D	@ 18000000 8M   | vram (+ 2MB)
-    mov r10, #0x25
-    mov r11, #0x25
-    mov r12, #0x25
+    mov r8, #0x2D
     mcr p15, 0, r0, c6, c0, 0
     mcr p15, 0, r1, c6, c1, 0
     mcr p15, 0, r2, c6, c2, 0
@@ -69,9 +67,9 @@ _start:
     mcr p15, 0, r5, c6, c5, 0
     mcr p15, 0, r6, c6, c6, 0
     mcr p15, 0, r7, c6, c7, 0
-    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
+    mcr p15, 0, r8, c3, c0, 0	@ Write bufferable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 0	@ Data cacheable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 1	@ Inst cacheable 0, 2, 5
 
     @ Enable dctm
     ldr r1, =0x3000800A        @ set dtcm