From 793754016231c23763a69a912ddf25196a34cae3 Mon Sep 17 00:00:00 2001 From: Wolfvak Date: Thu, 26 Oct 2017 20:27:02 -0300 Subject: [PATCH] Entrypoint detection stuff (untested) --- common/entrypoints.h | 7 +++ source/main.c | 2 +- source/start.s | 131 +++++++++++++++++++++++++++++-------------- 3 files changed, 96 insertions(+), 44 deletions(-) create mode 100644 common/entrypoints.h diff --git a/common/entrypoints.h b/common/entrypoints.h new file mode 100644 index 0000000..e673864 --- /dev/null +++ b/common/entrypoints.h @@ -0,0 +1,7 @@ +#pragma once + +#define ENTRY_UNKNOWN (0) +#define ENTRY_B9S (1) +#define ENTRY_NTRBOOT (2) +#define ENTRY_NANDBOOT (3) +#define ENTRY_SPIBOOT (4) diff --git a/source/main.c b/source/main.c index 15843ab..b50e1a9 100644 --- a/source/main.c +++ b/source/main.c @@ -3,7 +3,7 @@ #include "pxi.h" #include "i2c.h" -void main(int argc, char** argv) +void main(int argc, char** argv, int entrypoint) { (void) argv; // unused for now diff --git a/source/start.s b/source/start.s index f36fb84..d6b60cc 100644 --- a/source/start.s +++ b/source/start.s @@ -4,6 +4,7 @@ #include #include +#include .global _start _start: @@ -13,9 +14,10 @@ _start: msr cpsr_c, r4 @ Preserve boot registers - mov r9, r0 - mov r10, r1 - mov r11, r2 + mov r8, r0 + mov r9, r1 + mov r10, r2 + mov r11, r3 @ Clear bss ldr r0, =__bss_start @@ -46,33 +48,29 @@ _start: mcr p15, 0, r0, c5, c0, 3 @ write instruction access @ Set MPU regions and cache settings - adr r0, __mpu_regions - ldmia r0, {r1-r8} - mov r0, #0b00101000 - mcr p15, 0, r1, c6, c0, 0 - mcr p15, 0, r2, c6, c1, 0 - mcr p15, 0, r3, c6, c2, 0 - mcr p15, 0, r4, c6, c3, 0 - mcr p15, 0, r5, c6, c4, 0 - mcr p15, 0, r6, c6, c5, 0 - mcr p15, 0, r7, c6, c6, 0 - mcr p15, 0, r8, c6, c7, 0 - mcr p15, 0, r0, c3, c0, 0 @ Write bufferable - mcr p15, 0, r0, c2, c0, 0 @ Data cacheable - mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable + ldr lr, =__mpu_regions + ldmia lr, {r0-r7} + mov lr, #0b00101000 + mcr p15, 0, r0, c6, c0, 0 + mcr p15, 0, r1, c6, c1, 0 + mcr p15, 0, r2, c6, c2, 0 + mcr p15, 0, r3, c6, c3, 0 + mcr p15, 0, r4, c6, c4, 0 + mcr p15, 0, r5, c6, c5, 0 + mcr p15, 0, r6, c6, c6, 0 + mcr p15, 0, r7, c6, c7, 0 + mcr p15, 0, lr, c3, c0, 0 @ Write bufferable + mcr p15, 0, lr, c2, c0, 0 @ Data cacheable + mcr p15, 0, lr, c2, c0, 1 @ Inst cacheable - @ Enable dctm + @ Enable DTCM ldr r0, =0x3000800A mcr p15, 0, r0, c9, c1, 0 @ set the DTCM Region Register - @ Enable caches / select low exception vectors - ldr r1, =(CR_ALT_VECTORS | CR_DISABLE_TBIT) - ldr r2, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \ - CR_ENABLE_DTCM | CR_CACHE_RROBIN) - mrc p15, 0, r0, c1, c0, 0 - bic r0, r1 - orr r0, r2 - mcr p15, 0, r0, c1, c0, 0 + @ Fix SDMC mounting + mov r0, #0x10000000 + mov r1, #0x340 + str r1, [r0, #0x20] @ Install exception handlers ldr r0, =XRQ_Start @@ -84,31 +82,78 @@ _start: strlo r3, [r2], #4 blo .LXRQ_Install - @ Fix SDMC mounting - mov r0, #0x10000000 - mov r1, #0x340 - str r1, [r0, #0x20] - - @ Check arguments - lsl r2, r11, #16 - lsr r2, r2, #16 - - ldr r3, =0xBEEF - cmp r2, r3 - - moveq r0, r9 - moveq r1, r10 - movne r0, #0 + @ Enable caches / DTCM / select low exception vectors + ldr r1, =(CR_ALT_VECTORS | CR_DISABLE_TBIT) + ldr r2, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \ + CR_ENABLE_DTCM | CR_CACHE_RROBIN) + mrc p15, 0, r0, c1, c0, 0 + bic r0, r1 + orr r0, r2 + mcr p15, 0, r0, c1, c0, 0 @ Switch to system mode, disable interrupts, setup application stack msr cpsr_c, #(SR_SYS_MODE | SR_IRQ | SR_FIQ) ldr sp, =__stack_top - b main + + @ Check entrypoints + + @ b9s + ldr r3, =0xBEEF + lsl r2, r10, #16 + lsr r2, r2, #16 + cmp r2, r3 + + moveq r0, r8 + moveq r1, r9 + moveq r2, #(ENTRY_B9S) + beq .Lboot_main + + @ ntrboot + ldr r4, =0x1FFFE00C + ldr r5, =0x1FFFE010 + + ldrd r6, r7, [r5] + orr r6, r6, r7 + cmp r6, #0 + ldreqb r6, [r4, #1] + ldreqb r7, [r4, #3] + cmpeq r6, #0 + cmpeq r7, #2 + + moveq r0, #0 + moveq r1, #0 + moveq r2, #(ENTRY_NTRBOOT) + beq .Lboot_main + + @ nandboot + ldrd r6, r7, [r5] + orr r6, r6, r7 + cmp r6, #0 + beq .Lentrycheck_firmboot_end + ldrb r6, [r4, #0] + cmp r6, #0 + moveq r0, #0 + moveq r1, #0 + moveq r2, #(ENTRY_NANDBOOT) + beq .Lboot_main +.Lentrycheck_firmboot_end: + + @ Unknown + mov r0, #0 + mov r1, #0 + mov r2, #(ENTRY_UNKNOWN) + + +.Lboot_main: + ldr r3, =main + mov lr, #0 + bx r3 + __mpu_regions: .word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected) .word 0x3000801B @ 30008000 16k | dtcm - .word 0x00000035 @ 00000000 128M | itcm + .word 0x00000035 @ 00000000 128M | itcm (+ mirrors) .word 0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS) .word 0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB) .word 0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)