forked from Mirror/GodMode9
016eac6982
- maps a regular ARM-style exception vector table instead of using the bootrom vector redirection features a ton of bugs because I'm missing something, it actually manages to boot fb3DS v1.2 and BAX fine, but fails to boot itself
324 lines
6.2 KiB
C
324 lines
6.2 KiB
C
#pragma once
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#include "types.h"
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/* Status Register flags */
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#define SR_USR_MODE (0x10)
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#define SR_FIQ_MODE (0x11)
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#define SR_IRQ_MODE (0x12)
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#define SR_SVC_MODE (0x13)
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#define SR_ABT_MODE (0x17)
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#define SR_UND_MODE (0x1B)
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#define SR_SYS_MODE (0x1F)
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#define SR_PMODE_MASK (0x1F)
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#define SR_THUMB BIT(5)
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#define SR_NOFIQ BIT(6)
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#define SR_NOIRQ BIT(7)
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#define SR_NOINT (SR_NOFIQ | SR_NOIRQ)
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#ifdef ARM9
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#define CR_MPU BIT(0)
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#define CR_DCACHE BIT(2)
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#define CR_ICACHE BIT(12)
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#define CR_DTCM BIT(16)
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#define CR_ITCM BIT(18)
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#define CR_V4TLD BIT(15)
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#define CR_ALT_VECTORS BIT(13)
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#define CR_CACHE_RROBIN BIT(14)
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#define CR_DTCM_LOAD BIT(17)
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#define CR_ITCM_LOAD BIT(19)
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#define CR_TCM_LOAD (CR_DTCM_LOAD | CR_ITCM_LOAD)
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#define ICACHE_SZ (4096)
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#define DCACHE_SZ (4096)
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#define MAX_IRQ (32)
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#define MAX_CPU (1)
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#else // ARM11
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#define CR_MMU BIT(0)
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#define CR_ALIGN BIT(1)
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#define CR_DCACHE BIT(2)
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#define CR_ICACHE BIT(12)
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#define CR_FLOWPRED BIT(11)
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#define CR_HIGHVEC BIT(13)
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#define CR_V4TLD BIT(15)
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#define CR_UNALIGN BIT(22)
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#define CR_DSUBPAGE BIT(23)
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#define ACR_RETSTK BIT(0)
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#define ACR_DBPRED BIT(1)
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#define ACR_SBPRED BIT(2)
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#define ACR_FOLDING BIT(3)
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#define ACR_EXCL BIT(4)
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#define ACR_SMP BIT(5)
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#define ICACHE_SZ (16384)
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#define DCACHE_SZ (16384)
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#define MAX_IRQ (224)
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#define MAX_CPU (1)
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#endif
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#define CR_CACHES (CR_DCACHE | CR_ICACHE)
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#ifndef __ASSEMBLER__
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/* ARM Private Memory Region */
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#ifdef ARM11
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#define REG_ARM_PMR(off, type) ((volatile type*)(0x17E00000 + (off)))
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#endif
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#define ARM_MCR(cp, op1, reg, crn, crm, op2) asm_v( \
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"MCR " #cp ", " #op1 ", %[R], " #crn ", " #crm ", " #op2 "\n\t" \
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:: [R] "r"(reg))
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#define ARM_MRC(cp, op1, reg, crn, crm, op2) asm_v( \
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"MRC " #cp ", " #op1 ", %[R], " #crn ", " #crm ", " #op2 "\n\t" \
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: [R] "=r"(reg))
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#define ARM_MSR(cp, reg) asm_v( \
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"MSR " #cp ", %[R]\n\t" \
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:: [R] "r"(reg))
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#define ARM_MRS(reg, cp) asm_v( \
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"MRS %[R], " #cp "\n\t" \
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: [R] "=r"(reg))
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#ifdef ARM11
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#define ARM_CPS(m) asm_v("CPS " #m)
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#define ARM_CPSID(m) asm_v("CPSID " #m)
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#define ARM_CPSIE(m) asm_v("CPSIE " #m)
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/*
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* An Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor
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* so that all instructions following the ISB are fetched from cache or memory
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* after the ISB has been completed.
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*/
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static inline void ARM_ISB(void) {
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ARM_MCR(p15, 0, 0, c7, c5, 4);
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}
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/*
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* A Data Memory Barrier (DMB) ensures that all explicit memory accesses before
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* the DMB instruction complete before any explicit memory accesses after the DMB instruction start.
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*/
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static inline void ARM_DMB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 5);
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}
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/* Wait For Interrupt */
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static inline void ARM_WFI(void) {
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asm_v("wfi\n\t");
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}
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/* Wait For Event */
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static inline void ARM_WFE(void) {
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asm_v("wfe\n\t");
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}
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/* Send Event */
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static inline void ARM_SEV(void) {
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asm_v("sev\n\t");
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}
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/* Auxiliary Control Registers */
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static inline u32 ARM_GetACR(void) {
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u32 acr;
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ARM_MRC(p15, 0, acr, c1, c0, 1);
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return acr;
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}
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static inline void ARM_SetACR(u32 acr) {
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ARM_MCR(p15, 0, acr, c1, c0, 1);
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}
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#endif
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/*
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* A Data Synchronization Barrier (DSB) completes when all
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* instructions before this instruction complete.
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*/
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static inline void ARM_DSB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 4);
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}
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/* Control Registers */
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static inline u32 ARM_GetCR(void) {
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u32 cr;
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ARM_MRC(p15, 0, cr, c1, c0, 0);
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return cr;
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}
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static inline void ARM_SetCR(u32 cr) {
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ARM_MCR(p15, 0, cr, c1, c0, 0);
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}
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/* Thread ID Registers */
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static inline u32 ARM_GetTID(void) {
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u32 pid;
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#ifdef ARM9
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ARM_MRC(p15, 0, pid, c13, c0, 1);
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#else
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ARM_MRC(p15, 0, pid, c13, c0, 4);
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#endif
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return pid;
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}
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static inline void ARM_SetTID(u32 pid) {
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#ifdef ARM9
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ARM_MCR(p15, 0, pid, c13, c0, 1);
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#else
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ARM_MCR(p15, 0, pid, c13, c0, 4);
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#endif
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}
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/* CPU ID */
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static inline u32 ARM_CoreID(void) {
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u32 id;
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#ifdef ARM9
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id = 0;
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#else
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ARM_MRC(p15, 0, id, c0, c0, 5);
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#endif
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return id & 3;
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}
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/* Status Register */
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static inline u32 ARM_GetCPSR(void) {
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u32 sr;
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ARM_MRS(sr, cpsr);
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return sr;
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}
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static inline void ARM_SetCPSR_c(u32 sr) {
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ARM_MSR(cpsr_c, sr);
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}
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static inline void ARM_DisableInterrupts(void) {
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#ifdef ARM9
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ARM_SetCPSR_c(ARM_GetCPSR() | SR_NOINT);
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#else
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ARM_CPSID(if);
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#endif
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}
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static inline void ARM_EnableInterrupts(void) {
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#ifdef ARM9
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ARM_SetCPSR_c(ARM_GetCPSR() & ~SR_NOINT);
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#else
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ARM_CPSIE(if);
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#endif
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}
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static inline u32 ARM_EnterCritical(void) {
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u32 stat = ARM_GetCPSR();
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ARM_DisableInterrupts();
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return stat & SR_NOINT;
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}
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static inline void ARM_LeaveCritical(u32 stat) {
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ARM_SetCPSR_c((ARM_GetCPSR() & ~SR_NOINT) | stat);
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}
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/* Cache functions */
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static inline void ARM_InvIC(void) {
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#ifdef ARM9
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ARM_MCR(p15, 0, 0, c7, c5, 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c7, 0);
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#endif
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}
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static inline void ARM_InvIC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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#ifdef ARM9
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ARM_MCR(p15, 0, addr, c7, c5, 1);
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#else
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ARM_MCR(p15, 0, addr, c7, c7, 1);
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#endif
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addr += 0x20;
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} while(len--);
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}
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static inline void ARM_InvDC(void) {
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ARM_MCR(p15, 0, 0, c7, c6, 0);
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}
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static inline void ARM_InvDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c6, 1);
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addr += 0x20;
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} while(len--);
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}
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static inline void ARM_WbDC(void) {
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#ifdef ARM9
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u32 seg = 0, ind;
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do {
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ind = 0;
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do {
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ARM_MCR(p15, 0, seg | ind, c7, c10, 2);
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ind += 0x20;
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} while(ind < 0x400);
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seg += 0x40000000;
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} while(seg != 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c10, 0);
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#endif
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}
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static inline void ARM_WbDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c10, 1);
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addr += 0x20;
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} while(len--);
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}
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static inline void ARM_WbInvDC(void) {
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#ifdef ARM9
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u32 seg = 0, ind;
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do {
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ind = 0;
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do {
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ARM_MCR(p15, 0, seg | ind, c7, c14, 2);
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ind += 0x20;
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} while(ind < 0x400);
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seg += 0x40000000;
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} while(seg != 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c14, 0);
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#endif
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}
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static inline void ARM_WbInvDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c14, 1);
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addr += 0x20;
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} while(len--);
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}
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static inline void ARM_BKPT(void) {
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__builtin_trap();
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}
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#endif // __ASSEMBLER__
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