2017-08-08 09:40:09 -03:00
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/*
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Written by Wolfvak, specially sublicensed under the GPLv2
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Read LICENSE for more details
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*/
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#pragma once
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#include <types.h>
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#define asm __asm volatile
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static inline u32 CPU_ReadCPSR(void)
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{
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u32 cpsr;
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asm("mrs %0, cpsr\n\t":"=r"(cpsr));
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return cpsr;
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}
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static inline void CPU_WriteCPSR_c(u32 cpsr)
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{
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asm("msr cpsr_c, %0\n\t"::"r"(cpsr));
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return;
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}
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static inline u32 CPU_ReadCR(void)
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{
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u32 cr;
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asm("mrc p15, 0, %0, c1, c0, 0\n\t":"=r"(cr));
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return cr;
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}
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static inline void CPU_WriteCR(u32 cr)
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{
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asm("mcr p15, 0, %0, c1, c0, 0\n\t"::"r"(cr));
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return;
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}
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static inline void CPU_DisableIRQ(void)
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{
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#ifdef ARM9
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2017-08-12 16:04:20 -03:00
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CPU_WriteCPSR_c(CPU_ReadCPSR() | (SR_IRQ | SR_FIQ));
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2017-08-08 09:40:09 -03:00
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#else
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asm("cpsid if\n\t");
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#endif
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return;
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}
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static inline void CPU_EnableIRQ(void)
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{
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#ifdef ARM9
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2017-08-12 16:04:20 -03:00
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CPU_WriteCPSR_c(CPU_ReadCPSR() & ~(SR_IRQ | SR_FIQ));
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2017-08-08 09:40:09 -03:00
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#else
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asm("cpsie if\n\t");
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#endif
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return;
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}
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static inline void CPU_EnterCritical(u32 *ss)
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{
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*ss = CPU_ReadCPSR();
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CPU_DisableIRQ();
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return;
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}
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static inline void CPU_LeaveCritical(u32 *ss)
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{
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CPU_WriteCPSR_c(*ss);
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return;
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}
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