mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 21:52:48 +00:00
Merge pull request #4 from d0k3/new_ep_setup
Revised entrypoint linker.ld / start.s
This commit is contained in:
d0k3
commit
018f0fd65c
134
bootstrap.ld
134
bootstrap.ld
@ -1,130 +1,12 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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MEMORY
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{
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ram : ORIGIN = 0x23F00000, LENGTH = 128K
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}
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SECTIONS
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{
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.init :
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{
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__text_start = . ;
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KEEP (*(.init))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.plt : { *(.plt) } >ram = 0xff
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.text : /* ALIGN (4): */
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{
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*(.text .stub .text.* .gnu.linkonce.t.*)
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KEEP (*(.text.*personality*))
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning)
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*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.fini :
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{
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KEEP (*(.fini))
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} >ram =0xff
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__text_end = . ;
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.rodata :
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{
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*(.rodata)
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*all.rodata*(*)
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*(.roda)
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*(.rodata.*)
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*(.gnu.linkonce.r*)
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SORT(CONSTRUCTORS)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ram
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__exidx_start = .;
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.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >ram
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__exidx_end = .;
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/* Ensure the __preinit_array_start label is properly aligned. We
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could instead move the label definition inside the section, but
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the linker would then create the section even if it turns out to
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be empty, which isn't pretty. */
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. = ALIGN(32 / 8);
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PROVIDE (__preinit_array_start = .);
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.preinit_array : { KEEP (*(.preinit_array)) } >ram = 0xff
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PROVIDE (__preinit_array_end = .);
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PROVIDE (__init_array_start = .);
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.init_array : { KEEP (*(.init_array)) } >ram = 0xff
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PROVIDE (__init_array_end = .);
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PROVIDE (__fini_array_start = .);
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.fini_array : { KEEP (*(.fini_array)) } >ram = 0xff
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PROVIDE (__fini_array_end = .);
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of the constructors, so
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we make sure it is first. Because this is a wildcard, it
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doesn't matter if the user does not actually link against
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crtbegin.o; the linker won't look for a file to match a
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wildcard. The wildcard also means that it doesn't matter which
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directory crtbegin.o is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.eh_frame :
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{
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KEEP (*(.eh_frame))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.gcc_except_table :
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{
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*(.gcc_except_table)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.jcr : { KEEP (*(.jcr)) } >ram = 0
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.got : { *(.got.plt) *(.got) } >ram = 0
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.data ALIGN(4) : {
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d*)
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CONSTRUCTORS
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. = ALIGN(4);
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__data_end = ABSOLUTE(.) ;
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} >ram = 0xff
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.bss ALIGN(4) :
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{
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__bss_start = ABSOLUTE(.);
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__bss_start__ = ABSOLUTE(.);
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*(.dynbss)
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*(.gnu.linkonce.b*)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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__bss_end__ = ABSOLUTE(.);
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__end__ = ABSOLUTE(.);
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} >ram
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.stack 0x80000 : { _stack = .; *(.stack) }
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. = 0x23F00000;
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.text.start : { *(.text.start) }
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.text : { *(.text) }
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.data : { *(.data) }
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.bss : { *(.bss COMMON) }
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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__end__ = ABSOLUTE(.);
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}
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134
gateway.ld
134
gateway.ld
@ -1,130 +1,12 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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MEMORY
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{
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ram : ORIGIN = 0x08000000, LENGTH = 128K
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}
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SECTIONS
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{
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.init :
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{
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__text_start = . ;
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KEEP (*(.init))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.plt : { *(.plt) } >ram = 0xff
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.text : /* ALIGN (4): */
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{
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*(.text .stub .text.* .gnu.linkonce.t.*)
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KEEP (*(.text.*personality*))
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning)
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*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.fini :
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{
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KEEP (*(.fini))
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} >ram =0xff
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__text_end = . ;
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.rodata :
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{
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*(.rodata)
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*all.rodata*(*)
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*(.roda)
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*(.rodata.*)
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*(.gnu.linkonce.r*)
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SORT(CONSTRUCTORS)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ram
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__exidx_start = .;
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.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >ram
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__exidx_end = .;
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/* Ensure the __preinit_array_start label is properly aligned. We
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could instead move the label definition inside the section, but
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the linker would then create the section even if it turns out to
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be empty, which isn't pretty. */
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. = ALIGN(32 / 8);
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PROVIDE (__preinit_array_start = .);
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.preinit_array : { KEEP (*(.preinit_array)) } >ram = 0xff
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PROVIDE (__preinit_array_end = .);
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PROVIDE (__init_array_start = .);
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.init_array : { KEEP (*(.init_array)) } >ram = 0xff
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PROVIDE (__init_array_end = .);
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PROVIDE (__fini_array_start = .);
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.fini_array : { KEEP (*(.fini_array)) } >ram = 0xff
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PROVIDE (__fini_array_end = .);
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of the constructors, so
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we make sure it is first. Because this is a wildcard, it
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doesn't matter if the user does not actually link against
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crtbegin.o; the linker won't look for a file to match a
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wildcard. The wildcard also means that it doesn't matter which
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directory crtbegin.o is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.eh_frame :
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{
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KEEP (*(.eh_frame))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.gcc_except_table :
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{
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*(.gcc_except_table)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ram = 0xff
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.jcr : { KEEP (*(.jcr)) } >ram = 0
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.got : { *(.got.plt) *(.got) } >ram = 0
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.data ALIGN(4) : {
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d*)
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CONSTRUCTORS
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. = ALIGN(4);
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__data_end = ABSOLUTE(.) ;
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} >ram = 0xff
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.bss ALIGN(4) :
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{
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__bss_start = ABSOLUTE(.);
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__bss_start__ = ABSOLUTE(.);
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*(.dynbss)
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*(.gnu.linkonce.b*)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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__bss_end__ = ABSOLUTE(.);
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__end__ = ABSOLUTE(.);
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} >ram
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.stack 0x80000 : { _stack = .; *(.stack) }
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. = 0x08000000;
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.text.start : { *(.text.start) }
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.text : { *(.text) }
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.data : { *(.data) }
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.bss : { *(.bss COMMON) }
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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__end__ = ABSOLUTE(.);
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}
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@ -1,20 +1,18 @@
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#ifdef EXEC_BOOTSTRAP
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.section ".init"
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.global _start
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.extern main
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.section .text.start
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.align 4
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.arm
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.global _start
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_start:
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@ Change the stack pointer
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mov sp, #0x27000000
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@ Give read/write access to all the memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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ldr r5, =0x33333333
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mcr p15, 0, r5, c5, c0, 2 @ write data access
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mcr p15, 0, r5, c5, c0, 3 @ write instruction access
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@ Set MPU permissions and cache settings
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@ Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k
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ldr r1, =0x01FF801D @ 01ff8000 32k
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ldr r2, =0x08000027 @ 08000000 1M
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@ -23,6 +21,9 @@ _start:
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ldr r5, =0x20000035 @ 20000000 128M
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ldr r6, =0x1FF00027 @ 1FF00000 1M
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ldr r7, =0x1800002D @ 18000000 8M
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mov r10, #0x25
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mov r11, #0x25
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mov r12, #0x25
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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@ -31,24 +32,28 @@ _start:
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mov r0, #0x25
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mcr p15, 0, r0, c2, c0, 0 @ data cacheable
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mcr p15, 0, r0, c2, c0, 1 @ instruction cacheable
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mcr p15, 0, r0, c3, c0, 0 @ data bufferable
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mcr p15, 0, r10, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enable caches
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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orr r0, r0, #(1<<18) @ - itcm enable
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orr r0, r0, #(1<<12) @ - instruction cache enable
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orr r0, r0, #(1<<2) @ - data cache enable
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orr r0, r0, #(1<<0) @ - mpu enable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<18) @ - itcm enable
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Flush caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r0, c7, c6, 0 @ flush D-cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov r5, #0
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mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
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mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
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@ Fixes mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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bl main
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@ -1,11 +1,8 @@
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#ifdef EXEC_GATEWAY
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.section ".init"
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.section .text.start
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.global _start
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.extern main
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.align 4
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.align 4
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.arm
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_vectors:
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@ -40,6 +37,14 @@ _start:
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cmp r1, #0
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bgt waitLoop92
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@ Enable caches
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<18) @ - itcm enable
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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ldr sp,=0x22160000
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ldr r3, =main
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blx r3
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