mirror of
https://github.com/d0k3/GodMode9.git
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First viable(-ish) prototype
For some reason (messed up memory access?) the first two time I read the status register, I get garbage. Also: * Reinserting card breaks SPI (everything reads 0xff * No support for CTR carts for now
This commit is contained in:
Balint Kovacs
d0k3
parent
a3cc272e63
commit
2ceafc545b
@ -17,103 +17,42 @@
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*/
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#include "spi.h"
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#include "spicard.h"
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#include "ui.h"
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// Deliberately written in C! (except for a few lines)
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// u8* fill_buf = NULL;
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#define CFG_CARDCONF (*(vu16 *)0x1000000C)
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int SPIWriteRead(CardType type, void* cmd, u32 cmdSize, void* answer, u32 answerSize, void* data, u32 dataSize) {
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const u32 headerFooterVal = 0;
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bool b = type == FLASH_512KB_INFRARED || type == FLASH_256KB_INFRARED;
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#define REG_SPICARDCNT (*(vu32 *)0x1000D800)
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#define REG_SPICARDASSERT (*(vu32 *)0x1000D804)
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#define REG_SPICARDSIZE (*(vu32 *)0x1000D808)
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#define REG_SPICARDFIFO (*(vu32 *)0x1000D80C)
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#define REG_SPICARDFIFOSTAT (*(vu32 *)0x1000D810)
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#define REG_UNK_AT_0x18 (*(vu32 *)0x1000D818)
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SPICARD_init();
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#define SPICARD_START_IS_BUSY 0x8000
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//Thanks @Steveice10 for giving me his P9 symbols (IDB file).
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//This code is compatible with SPI.c/SPI.h from TWLSaveTool/// Card SPI baud rate.
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//taken over from ctrulib fs.h
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typedef enum {
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BAUDRATE_512KHZ = 0, ///< 512KHz.
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BAUDRATE_1MHZ = 1, ///< 1MHz.
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BAUDRATE_2MHZ = 2, ///< 2MHz.
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BAUDRATE_4MHZ = 3, ///< 4MHz.
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BAUDRATE_8MHZ = 4, ///< 8MHz.
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BAUDRATE_16MHZ = 5, ///< 16MHz.
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} FS_CardSpiBaudRate;
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void _SPITransferData(void *data, u32 len, FS_CardSpiBaudRate baudRate, bool write)
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{
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REG_SPICARDSIZE = len;
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REG_SPICARDCNT = (((write) ? 1 : 0) << 13) | (0 << 12) | (u32)baudRate;
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REG_UNK_AT_0x18 = 0;
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REG_SPICARDCNT |= SPICARD_START_IS_BUSY; //start
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u32 wordCount = (len + 3) >> 2;
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u32 len_was = len;
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for(u32 i = 0; i < wordCount; i++)
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{
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u32 nbBytes = (len <= 4) ? len : 4;
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if(write)
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{
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u32 word = 0;
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memcpy(&word, (u32 *)data + i, nbBytes);
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while(REG_SPICARDFIFOSTAT);
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REG_SPICARDFIFO = word;
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if (b) {
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SPICARD_writeRead(NSPI_CLK_1MHz, &headerFooterVal, NULL, 1, 0, false);
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}
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else
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{
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while(!REG_SPICARDFIFOSTAT);
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u32 word = REG_SPICARDFIFO;
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memcpy((u32 *)data + i, &word, nbBytes);
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}
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len -= nbBytes;
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}
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while(REG_SPICARDCNT & SPICARD_START_IS_BUSY) ShowString("Busy, %s %lu", (write) ? "write" : "read", len_was);
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}
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int SPIWriteRead(CardType type, void* cmd, u32 cmdSize, void* answer, u32 answerSize, void* data, u32 dataSize)
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{
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bool infra = type == FLASH_512KB_INFRARED || type == FLASH_256KB_INFRARED;
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CFG_CARDCONF |= 0x100; //wake card
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u32 zero = 0;
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if(infra) _SPITransferData(&zero, 1, BAUDRATE_1MHZ, true); //header
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if(cmd != NULL) _SPITransferData(cmd, cmdSize, BAUDRATE_4MHZ, true);
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if(answer != NULL) _SPITransferData(answer, answerSize, BAUDRATE_4MHZ, false);
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if(data != NULL) _SPITransferData(data, dataSize, BAUDRATE_4MHZ, true);
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if (dataSize) ShowPrompt(false, "Completed: %lu/%lu/%lu", cmdSize, answerSize, dataSize);
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// else ShowString("Completed: %lu/%lu/%lu", cmdSize, answerSize, dataSize);
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REG_SPICARDASSERT = 0;
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SPICARD_writeRead(NSPI_CLK_4MHz, cmd, answer, cmdSize, answerSize, false);
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SPICARD_writeRead(NSPI_CLK_4MHz, data, NULL, dataSize, 0, true);
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return 0;
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}
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int SPIWaitWriteEnd(CardType type) {
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u32 cmd = SPI_CMD_RDSR, statusReg = 0;
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u8 cmd = SPI_CMD_RDSR, statusReg = 0;
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int res = 0;
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ShowPrompt(false, "WaitWriteEnd start");
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do{
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res = SPIWriteRead(type, &cmd, 1, &statusReg, 1, 0, 0);
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if(res) return res;
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} while(statusReg & SPI_FLG_WIP);
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ShowPrompt(false, "WaitWriteEnd complete");
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return 0;
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}
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int SPIEnableWriting(CardType type) {
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u32 cmd = SPI_CMD_WREN, statusReg = 0;
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u8 cmd = SPI_CMD_WREN, statusReg = 0;
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int res = SPIWriteRead(type, &cmd, 1, NULL, 0, 0, 0);
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if(res || type == EEPROM_512B) return res; // Weird, but works (otherwise we're getting an infinite loop for that chip type).
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@ -128,9 +67,9 @@ int SPIEnableWriting(CardType type) {
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}
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int SPIReadJEDECIDAndStatusReg(CardType type, u32* id, u8* statusReg) {
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u32 cmd = SPI_FLASH_CMD_RDID;
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u32 reg = 0;
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u8 idbuf[4] = { 0 };
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u8 cmd = SPI_FLASH_CMD_RDID;
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u8 reg = 0;
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u8 idbuf[3] = { 0 };
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u32 id_ = 0;
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int res = SPIWaitWriteEnd(type);
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if(res) return res;
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@ -145,6 +84,8 @@ int SPIReadJEDECIDAndStatusReg(CardType type, u32* id, u8* statusReg) {
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if(id) *id = id_;
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if(statusReg) *statusReg = reg;
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ShowPrompt(false, "JEDEC = %lx, StatusReg = %hhx", *id, reg);
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return 0;
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}
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@ -409,6 +350,24 @@ int SPIGetCardType(CardType* type, int infrared) {
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while(tries < maxTries){
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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res = SPIReadJEDECIDAndStatusReg(t, &jedec, &sr); // dummy
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if(res) return res;
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if ((sr & 0xfd) == 0x00 && (jedec != 0x00ffffff)) { break; }
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if ((sr & 0xfd) == 0xF0 && (jedec == 0x00ffffff)) { t = EEPROM_512B; break; }
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@ -417,7 +376,7 @@ int SPIGetCardType(CardType* type, int infrared) {
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++tries;
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t = FLASH_INFRARED_DUMMY;
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}
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ShowPrompt(false, "JEDECID done");
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if(t == EEPROM_512B) { *type = t; return 0; }
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else if(t == EEPROM_STD_DUMMY) {
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bool mirrored = false;
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139
arm9/source/gamecart/spicard.c
Normal file
139
arm9/source/gamecart/spicard.c
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@ -0,0 +1,139 @@
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/*
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* This file is part of fastboot 3DS
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* Copyright (C) 2019 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "spicard.h"
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#include "delay.h"
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#define SPICARD_REGS_BASE 0x1000D800
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#define REG_NSPI_CNT *((vu32*)(SPICARD_REGS_BASE + 0x00))
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#define REG_NSPI_DONE *((vu32*)(SPICARD_REGS_BASE + 0x04))
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#define REG_NSPI_BLKLEN *((vu32*)(SPICARD_REGS_BASE + 0x08))
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#define REG_NSPI_FIFO *((vu32*)(SPICARD_REGS_BASE + 0x0C))
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#define REG_NSPI_STATUS *((vu32*)(SPICARD_REGS_BASE + 0x10))
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#define REG_NSPI_AUTOPOLL *((vu32*)(SPICARD_REGS_BASE + 0x14))
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#define REG_NSPI_INT_MASK *((vu32*)(SPICARD_REGS_BASE + 0x18))
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#define REG_NSPI_INT_STAT *((vu32*)(SPICARD_REGS_BASE + 0x1C))
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static inline void nspiWaitBusy(void)
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{
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while(REG_NSPI_CNT & NSPI_CNT_ENABLE);
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}
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static inline void nspiWaitFifoBusy(void)
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{
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while(REG_NSPI_STATUS & NSPI_STATUS_BUSY);
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}
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void SPICARD_init(void)
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{
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static bool inited = false;
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if(inited) return;
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inited = true;
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// TODO
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#define REG_CFG9_CARDCTL *((vu16*)0x1000000C)
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#define REG_CFG9_CARDSTATUS *((vu8* )0x10000010)
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#define REG_CFG9_CARDCYCLES0 *((vu16*)0x10000012)
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#define REG_CFG9_CARDCYCLES1 *((vu16*)0x10000014)
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#define REG_NTRCARDMCNT *((vu16*)0x10164000)
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#define REG_NTRCARDROMCNT *((vu32*)0x10164004)
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REG_CFG9_CARDCYCLES0 = 0x1988;
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REG_CFG9_CARDCYCLES1 = 0x264C;
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// boot9 waits here. Unnecessary?
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REG_CFG9_CARDSTATUS = 3u<<2; // Request power off
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while(REG_CFG9_CARDSTATUS != 0); // Aotomatically changes to 0 (off)
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ioDelay(1000);
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REG_CFG9_CARDSTATUS = 1u<<2; // Prepare power on
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ioDelay(10000);
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REG_CFG9_CARDSTATUS = 2u<<2; // Power on
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ioDelay(27000);
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// Switch to NTRCARD controller.
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REG_CFG9_CARDCTL = 0;
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REG_NTRCARDMCNT = 0xC000u;
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REG_NTRCARDROMCNT = 0x20000000;
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ioDelay(120000);
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REG_CFG9_CARDCTL |= 1u<<8;
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REG_NSPI_INT_MASK = NSPI_INT_TRANSF_END; // Disable interrupt 1
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REG_NSPI_INT_STAT = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_TRANSF_END; // Aknowledge
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}
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/*
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bool _SPICARD_autoPollBit(u32 params)
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{
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REG_NSPI_AUTOPOLL = NSPI_AUTOPOLL_START | params;
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u32 res;
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do
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{
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__wfi();
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res = REG_NSPI_INT_STAT;
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} while(!(res & (NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS)));
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REG_NSPI_INT_STAT = res; // Aknowledge
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return (res & NSPI_INT_AP_TIMEOUT) == 0; // Timeout error
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}
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*/
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void SPICARD_writeRead(NspiClk clk, const u32 *in, u32 *out, u32 inSize, u32 outSize, bool done)
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{
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const u32 cntParams = NSPI_CNT_ENABLE | NSPI_CNT_BUS_1BIT | clk;
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if(in)
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{
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REG_NSPI_BLKLEN = inSize;
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REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_WRITE;
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u32 counter = 0;
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do
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{
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if((counter & 31) == 0) nspiWaitFifoBusy();
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REG_NSPI_FIFO = *in++;
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counter += 4;
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} while(counter < inSize);
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nspiWaitBusy();
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}
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if(out)
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{
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REG_NSPI_BLKLEN = outSize;
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REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_READ;
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u32 counter = 0;
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do
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{
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if((counter & 31) == 0) nspiWaitFifoBusy();
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*out++ = REG_NSPI_FIFO;
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counter += 4;
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} while(counter < outSize);
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nspiWaitBusy();
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}
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if(done) REG_NSPI_DONE = NSPI_DONE;
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}
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96
arm9/source/gamecart/spicard.h
Normal file
96
arm9/source/gamecart/spicard.h
Normal file
@ -0,0 +1,96 @@
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#pragma once
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/*
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* This file is part of fastboot 3DS
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* Copyright (C) 2019 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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// REG_NSPI_CNT
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#define NSPI_CNT_BUS_1BIT (0u)
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#define NSPI_CNT_BUS_4BIT (1u<<12)
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#define NSPI_CNT_DIRE_READ (0u)
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#define NSPI_CNT_DIRE_WRITE (1u<<13)
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#define NSPI_CNT_ENABLE (1u<<15)
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// REG_NSPI_DONE
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#define NSPI_DONE (0u)
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// REG_NSPI_STATUS
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#define NSPI_STATUS_BUSY (1u)
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// REG_NSPI_AUTOPOLL
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#define NSPI_AUTOPOLL_START (1u<<31)
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// REG_NSPI_INT_MASK Bit set = disabled.
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// REG_NSPI_INT_STAT Status and aknowledge.
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#define NSPI_INT_TRANSF_END (1u) // Fires on (each?) auto poll try aswell
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#define NSPI_INT_AP_SUCCESS (1u<<1) // Auto poll
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#define NSPI_INT_AP_TIMEOUT (1u<<2) // Auto poll
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typedef enum
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{
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NSPI_CLK_512KHz = 0u,
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NSPI_CLK_1MHz = 1u,
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NSPI_CLK_2MHz = 2u,
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NSPI_CLK_4MHz = 3u,
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NSPI_CLK_8MHz = 4u,
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NSPI_CLK_16MHz = 5u
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} NspiClk;
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/**
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* @brief Initializes the SPI buses. Call this only once.
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*/
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void SPICARD_init(void);
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/**
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* @brief Automatically polls a bit of the command response. Use with the macro below.
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*
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* @param[in] params The parameters. Use the macro below.
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*
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* @return Returns false on failure/timeout and true on success.
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*/
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bool _SPICARD_autoPollBit(u32 params);
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/**
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* @brief Writes and/or reads data to/from a SPI device.
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*
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* @param[in] clk The clock frequency to use.
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* @param[in] in Input data pointer for write.
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* @param out Output data pointer for read.
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* @param[in] inSize Input size. Must be <= 0x1FFFFF.
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* @param[in] outSize Output size. Must be <= 0x1FFFFF.
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* @param[in] done Set to true if this is the last transfer (chip select).
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*/
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void SPICARD_writeRead(NspiClk clk, const u32 *in, u32 *out, u32 inSize, u32 outSize, bool done);
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/**
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* @brief Automatically polls a bit of the command response.
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*
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* @param[in] cmd The command.
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* @param[in] timeout The timeout. Must be 0-15. Tries = 31<<NspiClk + timeout.
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* @param[in] off The bit offset. Must be 0-7.
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* @param[in] bitSet Poll for a set ur unset bit.
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*
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* @return Returns false on failure/timeout and true on success.
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*/
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#define SPICARD_autoPollBit(cmd, timeout, off, bitSet) _SPICARD_autoPollBit((bitSet)<<30 | (off)<<24 | (timeout)<<16 | (cmd))
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