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Merge pull request #6 from d0k3/test2

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Fix virtual memory drive accesses
This commit is contained in:
d0k3 2016-04-22 15:50:49 +02:00
commit 34fbebebef
4 changed files with 84 additions and 12 deletions
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28
source/abstraction/bs-start.s
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@ -7,20 +7,27 @@ _start:
@ Change the stack pointer @ Change the stack pointer
mov sp, #0x27000000 mov sp, #0x27000000
@ Disable caches / mpu
mrc p15, 0, r4, c1, c0, 0 @ read control register
bic r4, #(1<<12) @ - instruction cache disable
bic r4, #(1<<2) @ - data cache disable
bic r4, #(1<<0) @ - mpu disable
mcr p15, 0, r4, c1, c0, 0 @ write control register
@ Give read/write access to all the memory regions @ Give read/write access to all the memory regions
ldr r5, =0x33333333 ldr r5, =0x33333333
mcr p15, 0, r5, c5, c0, 2 @ write data access mcr p15, 0, r5, c5, c0, 2 @ write data access
mcr p15, 0, r5, c5, c0, 3 @ write instruction access mcr p15, 0, r5, c5, c0, 3 @ write instruction access
@ Sets MPU permissions and cache settings @ Sets MPU permissions and cache settings
ldr r0, =0xFFFF001D @ ffff0000 32k ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
ldr r1, =0x01FF801D @ 01ff8000 32k ldr r1, =0x3000801B @ fff00000 16k | dtcm
ldr r2, =0x08000027 @ 08000000 1M ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
ldr r3, =0x10000021 @ 10000000 128k ldr r3, =0x08000029 @ 08000000 1M | arm9 mem (O3DS / N3DS)
ldr r4, =0x10100025 @ 10100000 512k ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
ldr r5, =0x20000035 @ 20000000 128M ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
ldr r6, =0x1FF00027 @ 1FF00000 1M ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
ldr r7, =0x1800002D @ 18000000 8M ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
mov r10, #0x25 mov r10, #0x25
mov r11, #0x25 mov r11, #0x25
mov r12, #0x25 mov r12, #0x25
@ -36,9 +43,14 @@ _start:
mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5 mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5
mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5 mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5
@ Enable dctm
ldr r1, =0x3000800A @ set dtcm
mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
@ Enable caches @ Enable caches
mrc p15, 0, r4, c1, c0, 0 @ read control register mrc p15, 0, r4, c1, c0, 0 @ read control register
orr r4, r4, #(1<<18) @ - itcm enable orr r4, r4, #(1<<18) @ - itcm enable
orr r4, r4, #(1<<16) @ - dtcm enable
orr r4, r4, #(1<<12) @ - instruction cache enable orr r4, r4, #(1<<12) @ - instruction cache enable
orr r4, r4, #(1<<2) @ - data cache enable orr r4, r4, #(1<<2) @ - data cache enable
orr r4, r4, #(1<<0) @ - mpu enable orr r4, r4, #(1<<0) @ - mpu enable

52
source/abstraction/gw-start.s
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@ -37,13 +37,65 @@ _start:
cmp r1, #0 cmp r1, #0
bgt waitLoop92 bgt waitLoop92
@ Disable caches / mpu
mrc p15, 0, r4, c1, c0, 0 @ read control register
bic r4, #(1<<12) @ - instruction cache disable
bic r4, #(1<<2) @ - data cache disable
bic r4, #(1<<0) @ - mpu disable
mcr p15, 0, r4, c1, c0, 0 @ write control register
@ Give read/write access to all the memory regions
ldr r5, =0x33333333
mcr p15, 0, r5, c5, c0, 2 @ write data access
mcr p15, 0, r5, c5, c0, 3 @ write instruction access
@ Sets MPU permissions and cache settings
ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
ldr r1, =0x3000801B @ fff00000 16k | dtcm
ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
ldr r3, =0x08000029 @ 08000000 1M | arm9 mem (O3DS / N3DS)
ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
mov r10, #0x25
mov r11, #0x25
mov r12, #0x25
mcr p15, 0, r0, c6, c0, 0
mcr p15, 0, r1, c6, c1, 0
mcr p15, 0, r2, c6, c2, 0
mcr p15, 0, r3, c6, c3, 0
mcr p15, 0, r4, c6, c4, 0
mcr p15, 0, r5, c6, c5, 0
mcr p15, 0, r6, c6, c6, 0
mcr p15, 0, r7, c6, c7, 0
mcr p15, 0, r10, c3, c0, 0 @ Write bufferable 0, 2, 5
mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5
mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5
@ Enable dctm
ldr r1, =0x3000800A @ set dtcm
mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
@ Enable caches @ Enable caches
mrc p15, 0, r4, c1, c0, 0 @ read control register mrc p15, 0, r4, c1, c0, 0 @ read control register
orr r4, r4, #(1<<18) @ - itcm enable orr r4, r4, #(1<<18) @ - itcm enable
orr r4, r4, #(1<<16) @ - dtcm enable
orr r4, r4, #(1<<12) @ - instruction cache enable orr r4, r4, #(1<<12) @ - instruction cache enable
orr r4, r4, #(1<<2) @ - data cache enable orr r4, r4, #(1<<2) @ - data cache enable
orr r4, r4, #(1<<0) @ - mpu enable orr r4, r4, #(1<<0) @ - mpu enable
mcr p15, 0, r4, c1, c0, 0 @ write control register mcr p15, 0, r4, c1, c0, 0 @ write control register
@ Flush caches
mov r5, #0
mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
@ Fixes mounting of SDMC
ldr r0, =0x10000020
mov r1, #0x340
str r1, [r0]
ldr sp,=0x22160000 ldr sp,=0x22160000
ldr r3, =main ldr r3, =main

10
source/nand/virtual.c
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@ -7,6 +7,7 @@
#define VFLAG_ON_NO3DS NAND_TYPE_NO3DS #define VFLAG_ON_NO3DS NAND_TYPE_NO3DS
#define VFLAG_ON_NAND (VFLAG_ON_O3DS | VFLAG_ON_N3DS | VFLAG_ON_NO3DS) #define VFLAG_ON_NAND (VFLAG_ON_O3DS | VFLAG_ON_N3DS | VFLAG_ON_NO3DS)
#define VFLAG_ON_MEMORY VRT_MEMORY #define VFLAG_ON_MEMORY VRT_MEMORY
#define VFLAG_N3DS_ONLY (1<<30)
#define VFLAG_NAND_SIZE (1<<31) #define VFLAG_NAND_SIZE (1<<31)
// see: http://3dbrew.org/wiki/Flash_Filesystem#NAND_structure // see: http://3dbrew.org/wiki/Flash_Filesystem#NAND_structure
@ -29,12 +30,15 @@ VirtualFile virtualFileTemplates[] = {
{ "sector0x96.bin" , 0x00012C00, 0x00000200, 0xFF, VFLAG_ON_NAND }, { "sector0x96.bin" , 0x00012C00, 0x00000200, 0xFF, VFLAG_ON_NAND },
{ "nand_hdr.bin" , 0x00000000, 0x00000200, 0xFF, VFLAG_ON_NAND }, { "nand_hdr.bin" , 0x00000000, 0x00000200, 0xFF, VFLAG_ON_NAND },
{ "itcm.mem" , 0x01FF8000, 0x00008000, 0xFF, VFLAG_ON_MEMORY }, { "itcm.mem" , 0x01FF8000, 0x00008000, 0xFF, VFLAG_ON_MEMORY },
{ "arm9internal.mem" , 0x08000000, 0x00100000, 0xFF, VFLAG_ON_MEMORY }, { "arm9.mem" , 0x08000000, 0x00100000, 0xFF, VFLAG_ON_MEMORY },
{ "arm9ext.mem" , 0x08010000, 0x00100000, 0xFF, VFLAG_ON_MEMORY | VFLAG_N3DS_ONLY },
{ "vram.mem" , 0x18000000, 0x00600000, 0xFF, VFLAG_ON_MEMORY }, { "vram.mem" , 0x18000000, 0x00600000, 0xFF, VFLAG_ON_MEMORY },
{ "dsp.mem" , 0x1FF00000, 0x00080000, 0xFF, VFLAG_ON_MEMORY }, { "dsp.mem" , 0x1FF00000, 0x00080000, 0xFF, VFLAG_ON_MEMORY },
{ "axiwram.mem" , 0x1FF80000, 0x00080000, 0xFF, VFLAG_ON_MEMORY }, { "axiwram.mem" , 0x1FF80000, 0x00080000, 0xFF, VFLAG_ON_MEMORY },
{ "fcram.mem" , 0x20000000, 0x08000000, 0xFF, VFLAG_ON_MEMORY }, { "fcram.mem" , 0x20000000, 0x08000000, 0xFF, VFLAG_ON_MEMORY },
{ "dtcm.mem" , 0xFFF00000, 0x00004000, 0xFF, VFLAG_ON_MEMORY }, { "fcramext.mem" , 0x28000000, 0x08000000, 0xFF, VFLAG_ON_MEMORY | VFLAG_N3DS_ONLY },
{ "dtcm.mem" , 0x30008000, 0x00004000, 0xFF, VFLAG_ON_MEMORY },
// { "bootrom.mem" , 0xFFFF0000, 0x00010000, 0xFF, VFLAG_ON_MEMORY },
{ "bootrom_unp.mem" , 0xFFFF0000, 0x00008000, 0xFF, VFLAG_ON_MEMORY } { "bootrom_unp.mem" , 0xFFFF0000, 0x00008000, 0xFF, VFLAG_ON_MEMORY }
}; };
@ -95,6 +99,8 @@ bool FindVirtualFile(VirtualFile* vfile, const char* path, u32 size)
// process special flags // process special flags
if ((vfile->keyslot == 0x05) && !CheckSlot0x05Crypto()) if ((vfile->keyslot == 0x05) && !CheckSlot0x05Crypto())
return false; // keyslot 0x05 not properly set up return false; // keyslot 0x05 not properly set up
if ((vfile->flags & VFLAG_N3DS_ONLY) && (GetUnitPlatform() != PLATFORM_N3DS))
return false; // this is not on O3DS consoles
if (vfile->flags & VFLAG_NAND_SIZE) { if (vfile->flags & VFLAG_NAND_SIZE) {
if ((virtual_src != NAND_SYSNAND) && (GetNandSizeSectors(NAND_SYSNAND) != GetNandSizeSectors(virtual_src))) if ((virtual_src != NAND_SYSNAND) && (GetNandSizeSectors(NAND_SYSNAND) != GetNandSizeSectors(virtual_src)))
return false; // EmuNAND/IMGNAND is too small return false; // EmuNAND/IMGNAND is too small

6
source/nand/virtual.h
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@ -8,11 +8,13 @@
#define VRT_IMGNAND NAND_IMGNAND #define VRT_IMGNAND NAND_IMGNAND
#define VRT_MEMORY (1<<10) #define VRT_MEMORY (1<<10)
#define VFLAG_EXT_A9LH_AREA (1<<20)
static const char* virtualFileList[] = { // must have a match in virtualFileTemplates[] static const char* virtualFileList[] = { // must have a match in virtualFileTemplates[]
"twln.bin", "twlp.bin", "agbsave.bin", "firm0.bin", "firm1.bin", "ctrnand_fat.bin", "twln.bin", "twlp.bin", "agbsave.bin", "firm0.bin", "firm1.bin", "ctrnand_fat.bin",
"ctrnand_full.bin", "nand.bin", "nand_minsize.bin", "nand_hdr.bin", "sector0x96.bin", "ctrnand_full.bin", "nand.bin", "nand_minsize.bin", "nand_hdr.bin", "sector0x96.bin",
"itcm.mem", "arm9internal.mem", "vram.mem", "dsp.mem", "axiwram.mem", "fcram.mem", "itcm.mem", "arm9.mem", "arm9ext.mem", "vram.mem", "dsp.mem", "axiwram.mem",
"dtcm.mem", "bootrom_unp.mem" "fcram.mem", "fcramext.mem", "dtcm.mem", "bootrom_unp.mem"
}; };
static const u32 virtualFileList_size = sizeof(virtualFileList) / sizeof(char*); static const u32 virtualFileList_size = sizeof(virtualFileList) / sizeof(char*);