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Updated sdmmc.c driver with support for faster reading/writing

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thanks @profi200
This commit is contained in:
d0k3 2018-05-29 01:59:59 +02:00
parent 5b72bfdf16
commit 568db1d471
6 changed files with 657 additions and 457 deletions
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16
arm9/source/nand/delay.s
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@ -1,16 +0,0 @@
.text
.arm
.align 4
.global waitcycles
.type waitcycles, %function
waitcycles:
push {r0-r2, lr}
str r0, [sp, #4]
waitcycles_loop:
ldr r3, [sp, #4]
subs r2, r3, #1
str r2, [sp, #4]
cmp r3, #0
bne waitcycles_loop
pop {r0-r2, pc}

876
arm9/source/nand/sdmmc.c
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@ -1,6 +1,6 @@
/* /*
* This Source Code Form is subject to the terms of the Mozilla Public * This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this file, * License, v. 2.0. If a copy of the MPL was not distributed with this file,
* You can obtain one at http://mozilla.org/MPL/2.0/. * You can obtain one at http://mozilla.org/MPL/2.0/.
* *
* Copyright (c) 2014-2015, Normmatt * Copyright (c) 2014-2015, Normmatt
@ -22,479 +22,599 @@
* along with this program. If not, see http://www.gnu.org/licenses/. * along with this program. If not, see http://www.gnu.org/licenses/.
*/ */
#include <stdint.h>
#include <stdbool.h>
#include "timer.h"
#include "wait.h"
#include "sdmmc.h" #include "sdmmc.h"
#include "delay.h"
static struct mmcdevice handleNAND; #define DATA32_SUPPORT
static struct mmcdevice handleSD;
static inline u16 sdmmc_read16(u16 reg)
{
return *(vu16 *)(SDMMC_BASE + reg);
}
static inline void sdmmc_write16(u16 reg, u16 val) struct mmcdevice handleNAND;
{ struct mmcdevice handleSD;
*(vu16 *)(SDMMC_BASE + reg) = val;
}
static inline u32 sdmmc_read32(u16 reg)
{
return *(vu32 *)(SDMMC_BASE + reg);
}
static inline void sdmmc_write32(u16 reg, u32 val)
{
*(vu32 *)(SDMMC_BASE + reg) = val;
}
static inline void sdmmc_mask16(u16 reg, const u16 clear, const u16 set)
{
u16 val = sdmmc_read16(reg);
val &= ~clear;
val |= set;
sdmmc_write16(reg, val);
}
static inline void setckl(u32 data)
{
sdmmc_mask16(REG_SDCLKCTL, 0x100, 0);
sdmmc_mask16(REG_SDCLKCTL, 0x2FF, data & 0x2FF);
sdmmc_mask16(REG_SDCLKCTL, 0x0, 0x100);
}
mmcdevice *getMMCDevice(int drive) mmcdevice *getMMCDevice(int drive)
{ {
if(drive == 0) return &handleNAND; if(drive==0) return &handleNAND;
return &handleSD; return &handleSD;
} }
static int geterror(struct mmcdevice *ctx) static int get_error(struct mmcdevice *ctx)
{ {
return (int)((ctx->error << 29) >> 31); return (int)((ctx->error << 29) >> 31);
} }
static void inittarget(struct mmcdevice *ctx)
static void set_target(struct mmcdevice *ctx)
{ {
sdmmc_mask16(REG_SDPORTSEL, 0x3, (u16)ctx->devicenumber); sdmmc_mask16(REG_SDPORTSEL,0x3,(uint16_t)ctx->devicenumber);
setckl(ctx->clk); setckl(ctx->clk);
if(ctx->SDOPT == 0) sdmmc_mask16(REG_SDOPT, 0, 0x8000); if(ctx->SDOPT == 0)
else sdmmc_mask16(REG_SDOPT, 0x8000, 0); {
sdmmc_mask16(REG_SDOPT,0,0x8000);
}
else
{
sdmmc_mask16(REG_SDOPT,0x8000,0);
}
} }
static void __attribute__((noinline)) sdmmc_send_command(struct mmcdevice *ctx, u32 cmd, u32 args) static void sdmmc_send_command(struct mmcdevice *ctx, uint32_t cmd, uint32_t args)
{ {
u32 getSDRESP = (cmd << 15) >> 31; const bool getSDRESP = (cmd << 15) >> 31;
u16 flags = (cmd << 15) >> 31; uint16_t flags = (cmd << 15) >> 31;
const int readdata = cmd & 0x20000; const bool readdata = cmd & 0x20000;
const int writedata = cmd & 0x40000; const bool writedata = cmd & 0x40000;
if(readdata || writedata) if(readdata || writedata)
flags |= TMIO_STAT0_DATAEND; {
flags |= TMIO_STAT0_DATAEND;
}
ctx->error = 0; ctx->error = 0;
while((sdmmc_read16(REG_SDSTATUS1) & TMIO_STAT1_CMD_BUSY)); //mmc working? while((sdmmc_read16(REG_SDSTATUS1) & TMIO_STAT1_CMD_BUSY)); //mmc working?
sdmmc_write16(REG_SDIRMASK0, 0); sdmmc_write16(REG_SDIRMASK0,0);
sdmmc_write16(REG_SDIRMASK1, 0); sdmmc_write16(REG_SDIRMASK1,0);
sdmmc_write16(REG_SDSTATUS0, 0); sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1, 0); sdmmc_write16(REG_SDSTATUS1,0);
sdmmc_mask16(REG_DATACTL32, 0x1800, 0); sdmmc_mask16(REG_DATACTL32,0x1800,0x400); // Disable TX32RQ and RX32RDY IRQ. Clear fifo.
sdmmc_write16(REG_SDCMDARG0, args & 0xFFFF); sdmmc_write16(REG_SDCMDARG0,args &0xFFFF);
sdmmc_write16(REG_SDCMDARG1, args >> 16); sdmmc_write16(REG_SDCMDARG1,args >> 16);
sdmmc_write16(REG_SDCMD, cmd & 0xFFFF); sdmmc_write16(REG_SDCMD,cmd &0xFFFF);
u32 size = ctx->size; uint32_t size = ctx->size;
u8 *rDataPtr = ctx->rData; const uint16_t blkSize = sdmmc_read16(REG_SDBLKLEN32);
const u8 *tDataPtr = ctx->tData; u32 *rDataPtr32 = (u32*)(void*)ctx->rData;
u8 *rDataPtr8 = ctx->rData;
const u32 *tDataPtr32 = (u32*)(void*)ctx->tData;
const u8 *tDataPtr8 = ctx->tData;
bool rUseBuf = rDataPtr != NULL; bool rUseBuf = ( NULL != rDataPtr32 );
bool tUseBuf = tDataPtr != NULL; bool tUseBuf = ( NULL != tDataPtr32 );
u16 status0 = 0; uint16_t status0 = 0;
while(true) while(1)
{ {
vu16 status1 = sdmmc_read16(REG_SDSTATUS1); volatile uint16_t status1 = sdmmc_read16(REG_SDSTATUS1);
vu16 ctl32 = sdmmc_read16(REG_DATACTL32); #ifdef DATA32_SUPPORT
if((ctl32 & 0x100)) volatile uint16_t ctl32 = sdmmc_read16(REG_DATACTL32);
{ if((ctl32 & 0x100))
if(readdata) #else
{ if((status1 & TMIO_STAT1_RXRDY))
if(rUseBuf) #endif
{ {
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_RXRDY, 0); if(readdata)
if(size > 0x1FF) {
{ if(rUseBuf)
//Gabriel Marcano: This implementation doesn't assume alignment. {
//I've removed the alignment check doen with former rUseBuf32 as a result sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_RXRDY, 0);
for(int i = 0; i < 0x200; i += 4) if(size >= blkSize)
{ {
u32 data = sdmmc_read32(REG_SDFIFO32); #ifdef DATA32_SUPPORT
*rDataPtr++ = data; if(!((u32)rDataPtr32 & 3))
*rDataPtr++ = data >> 8; {
*rDataPtr++ = data >> 16; for(uint32_t i = 0; i < blkSize; i += 4)
*rDataPtr++ = data >> 24; {
} *rDataPtr32++ = sdmmc_read32(REG_SDFIFO32);
size -= 0x200; }
} }
} else
{
for(uint32_t i = 0; i < blkSize; i += 4)
{
u32 data = sdmmc_read32(REG_SDFIFO32);
*rDataPtr8++ = data;
*rDataPtr8++ = data >> 8;
*rDataPtr8++ = data >> 16;
*rDataPtr8++ = data >> 24;
}
}
#else
if(!((u32)rDataPtr16 & 1))
{
for(uint32_t i = 0; i < blkSize; i += 4)
{
*rDataPtr16++ = sdmmc_read16(REG_SDFIFO);
}
}
else
{
for(uint32_t i = 0; i < blkSize; i += 4)
{
u16 data = sdmmc_read16(REG_SDFIFO);
*rDataPtr8++ = data;
*rDataPtr8++ = data >> 8;
}
}
#endif
size -= blkSize;
}
}
sdmmc_mask16(REG_DATACTL32, 0x800, 0); sdmmc_mask16(REG_DATACTL32, 0x800, 0);
} }
} }
if(!(ctl32 & 0x200)) #ifdef DATA32_SUPPORT
{ if(!(ctl32 & 0x200))
if(writedata) #else
{ if((status1 & TMIO_STAT1_TXRQ))
if(tUseBuf) #endif
{ {
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_TXRQ, 0); if(writedata)
if(size > 0x1FF) {
{ if(tUseBuf)
for(int i = 0; i < 0x200; i += 4) {
{ sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_TXRQ, 0);
u32 data = *tDataPtr++; if(size >= blkSize)
data |= (u32)*tDataPtr++ << 8; {
data |= (u32)*tDataPtr++ << 16; #ifdef DATA32_SUPPORT
data |= (u32)*tDataPtr++ << 24; if(!((u32)tDataPtr32 & 3))
sdmmc_write32(REG_SDFIFO32, data); {
} for(uint32_t i = 0; i < blkSize; i += 4)
size -= 0x200; {
} sdmmc_write32(REG_SDFIFO32, *tDataPtr32++);
} }
}
else
{
for(uint32_t i = 0; i < blkSize; i += 4)
{
uint32_t data = *tDataPtr8++;
data |= (uint32_t)*tDataPtr8++ << 8;
data |= (uint32_t)*tDataPtr8++ << 16;
data |= (uint32_t)*tDataPtr8++ << 24;
sdmmc_write32(REG_SDFIFO32, data);
}
}
#else
if(!((u32)tDataPtr16 & 1))
{
for(uint32_t i = 0; i < blkSize; i += 2)
{
sdmmc_write16(REG_SDFIFO, *tDataPtr16++);
}
}
else
{
for(uint32_t i = 0; i < blkSize; i += 2)
{
uint16_t data = *tDataPtr8++;
data |= (uint16_t)(*tDataPtr8++ << 8);
sdmmc_write16(REG_SDFIFO, data);
}
}
#endif
size -= blkSize;
}
}
sdmmc_mask16(REG_DATACTL32, 0x1000, 0); sdmmc_mask16(REG_DATACTL32, 0x1000, 0);
} }
} }
if(status1 & TMIO_MASK_GW) if(status1 & TMIO_MASK_GW)
{ {
ctx->error |= 4; ctx->error |= 4;
break; break;
} }
if(!(status1 & TMIO_STAT1_CMD_BUSY)) if(!(status1 & TMIO_STAT1_CMD_BUSY))
{ {
status0 = sdmmc_read16(REG_SDSTATUS0); status0 = sdmmc_read16(REG_SDSTATUS0);
if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_CMDRESPEND) if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_CMDRESPEND)
{ {
ctx->error |= 0x1; ctx->error |= 0x1;
} }
if(status0 & TMIO_STAT0_DATAEND) if(status0 & TMIO_STAT0_DATAEND)
{ {
ctx->error |= 0x2; ctx->error |= 0x2;
} }
if((status0 & flags) == flags) if((status0 & flags) == flags)
break; break;
} }
} }
ctx->stat0 = sdmmc_read16(REG_SDSTATUS0); ctx->stat0 = sdmmc_read16(REG_SDSTATUS0);
ctx->stat1 = sdmmc_read16(REG_SDSTATUS1); ctx->stat1 = sdmmc_read16(REG_SDSTATUS1);
sdmmc_write16(REG_SDSTATUS0, 0); sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1, 0); sdmmc_write16(REG_SDSTATUS1,0);
if(getSDRESP != 0) if(getSDRESP != 0)
{ {
ctx->ret[0] = (u32)(sdmmc_read16(REG_SDRESP0) | (sdmmc_read16(REG_SDRESP1) << 16)); ctx->ret[0] = (uint32_t)(sdmmc_read16(REG_SDRESP0) | (sdmmc_read16(REG_SDRESP1) << 16));
ctx->ret[1] = (u32)(sdmmc_read16(REG_SDRESP2) | (sdmmc_read16(REG_SDRESP3) << 16)); ctx->ret[1] = (uint32_t)(sdmmc_read16(REG_SDRESP2) | (sdmmc_read16(REG_SDRESP3) << 16));
ctx->ret[2] = (u32)(sdmmc_read16(REG_SDRESP4) | (sdmmc_read16(REG_SDRESP5) << 16)); ctx->ret[2] = (uint32_t)(sdmmc_read16(REG_SDRESP4) | (sdmmc_read16(REG_SDRESP5) << 16));
ctx->ret[3] = (u32)(sdmmc_read16(REG_SDRESP6) | (sdmmc_read16(REG_SDRESP7) << 16)); ctx->ret[3] = (uint32_t)(sdmmc_read16(REG_SDRESP6) | (sdmmc_read16(REG_SDRESP7) << 16));
} }
} }
int __attribute__((noinline)) sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in) int sdmmc_sdcard_writesectors(uint32_t sector_no, uint32_t numsectors, const uint8_t *in)
{ {
if(handleSD.isSDHC == 0) sector_no <<= 9; if(handleSD.isSDHC == 0) sector_no <<= 9;
inittarget(&handleSD); set_target(&handleSD);
sdmmc_write16(REG_SDSTOP, 0x100); sdmmc_write16(REG_SDSTOP,0x100);
sdmmc_write16(REG_SDBLKCOUNT32, numsectors); #ifdef DATA32_SUPPORT
sdmmc_write16(REG_SDBLKLEN32, 0x200); sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
sdmmc_write16(REG_SDBLKCOUNT, numsectors); sdmmc_write16(REG_SDBLKLEN32,0x200);
handleSD.tData = in; #endif
handleSD.size = numsectors << 9; sdmmc_write16(REG_SDBLKCOUNT,numsectors);
sdmmc_send_command(&handleSD, 0x52C19, sector_no); handleSD.tData = in;
return geterror(&handleSD); handleSD.size = numsectors << 9;
sdmmc_send_command(&handleSD,0x52C19,sector_no);
return get_error(&handleSD);
} }
int __attribute__((noinline)) sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out) int sdmmc_sdcard_readsectors(uint32_t sector_no, uint32_t numsectors, uint8_t *out)
{ {
if(handleSD.isSDHC == 0) sector_no <<= 9; if(handleSD.isSDHC == 0) sector_no <<= 9;
inittarget(&handleSD); set_target(&handleSD);
sdmmc_write16(REG_SDSTOP, 0x100); sdmmc_write16(REG_SDSTOP,0x100);
sdmmc_write16(REG_SDBLKCOUNT32, numsectors); #ifdef DATA32_SUPPORT
sdmmc_write16(REG_SDBLKLEN32, 0x200); sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
sdmmc_write16(REG_SDBLKCOUNT, numsectors); sdmmc_write16(REG_SDBLKLEN32,0x200);
handleSD.rData = out; #endif
handleSD.size = numsectors << 9; sdmmc_write16(REG_SDBLKCOUNT,numsectors);
sdmmc_send_command(&handleSD, 0x33C12, sector_no); handleSD.rData = out;
return geterror(&handleSD); handleSD.size = numsectors << 9;
sdmmc_send_command(&handleSD,0x33C12,sector_no);
return get_error(&handleSD);
} }
int __attribute__((noinline)) sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out)
int sdmmc_nand_readsectors(uint32_t sector_no, uint32_t numsectors, uint8_t *out)
{ {
if(handleNAND.isSDHC == 0) sector_no <<= 9; if(handleNAND.isSDHC == 0) sector_no <<= 9;
inittarget(&handleNAND); set_target(&handleNAND);
sdmmc_write16(REG_SDSTOP, 0x100); sdmmc_write16(REG_SDSTOP,0x100);
sdmmc_write16(REG_SDBLKCOUNT32, numsectors); #ifdef DATA32_SUPPORT
sdmmc_write16(REG_SDBLKLEN32, 0x200); sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
sdmmc_write16(REG_SDBLKCOUNT, numsectors); sdmmc_write16(REG_SDBLKLEN32,0x200);
handleNAND.rData = out; #endif
handleNAND.size = numsectors << 9; sdmmc_write16(REG_SDBLKCOUNT,numsectors);
sdmmc_send_command(&handleNAND, 0x33C12, sector_no); handleNAND.rData = out;
inittarget(&handleSD); handleNAND.size = numsectors << 9;
return geterror(&handleNAND); sdmmc_send_command(&handleNAND,0x33C12,sector_no);
return get_error(&handleNAND);
} }
int __attribute__((noinline)) sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in) //experimental int sdmmc_nand_writesectors(uint32_t sector_no, uint32_t numsectors, const uint8_t *in) //experimental
{ {
if(handleNAND.isSDHC == 0) sector_no <<= 9; if(handleNAND.isSDHC == 0) sector_no <<= 9;
inittarget(&handleNAND); set_target(&handleNAND);
sdmmc_write16(REG_SDSTOP, 0x100); sdmmc_write16(REG_SDSTOP,0x100);
sdmmc_write16(REG_SDBLKCOUNT32, numsectors); #ifdef DATA32_SUPPORT
sdmmc_write16(REG_SDBLKLEN32, 0x200); sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
sdmmc_write16(REG_SDBLKCOUNT, numsectors); sdmmc_write16(REG_SDBLKLEN32,0x200);
handleNAND.tData = in; #endif
handleNAND.size = numsectors << 9; sdmmc_write16(REG_SDBLKCOUNT,numsectors);
sdmmc_send_command(&handleNAND, 0x52C19, sector_no); handleNAND.tData = in;
inittarget(&handleSD); handleNAND.size = numsectors << 9;
return geterror(&handleNAND); sdmmc_send_command(&handleNAND,0x52C19,sector_no);
return get_error(&handleNAND);
} }
static u32 calcSDSize(u8 *csd, int type) static uint32_t sdmmc_calc_size(uint8_t* csd, int type)
{ {
u32 result = 0; uint32_t result = 0;
if(type == -1) type = csd[14] >> 6; if(type == -1) type = csd[14] >> 6;
switch(type) switch(type)
{ {
case 0: case 0:
{ {
u32 block_len = csd[9] & 0xF; uint32_t block_len=csd[9]&0xf;
block_len = 1u << block_len; block_len=1u<<block_len;
u32 mult = (u32)((csd[4] >> 7) | ((csd[5] & 3) << 1)); uint32_t mult=( uint32_t)((csd[4]>>7)|((csd[5]&3)<<1));
mult = 1u << (mult + 2); mult=1u<<(mult+2);
result = csd[8] & 3; result=csd[8]&3;
result = (result << 8) | csd[7]; result=(result<<8)|csd[7];
result = (result << 2) | (csd[6] >> 6); result=(result<<2)|(csd[6]>>6);
result = (result + 1) * mult * block_len / 512; result=(result+1)*mult*block_len/512;
break; }
} break;
case 1: case 1:
result = csd[7] & 0x3F; result=csd[7]&0x3f;
result = (result << 8) | csd[6]; result=(result<<8)|csd[6];
result = (result << 8) | csd[5]; result=(result<<8)|csd[5];
result = (result + 1) * 1024; result=(result+1)*1024;
break; break;
default: default:
break; //Do nothing otherwise FIXME perhaps return some error? break; //Do nothing otherwise FIXME perhaps return some error?
} }
return result; return result;
} }
static void InitSD() void sdmmc_init()
{ {
*(vu16 *)0x10006100 &= 0xF7FFu; //SDDATACTL32 //NAND
*(vu16 *)0x10006100 &= 0xEFFFu; //SDDATACTL32 handleNAND.isSDHC = 0;
*(vu16 *)0x10006100 |= 0x402u; //SDDATACTL32 handleNAND.SDOPT = 0;
*(vu16 *)0x100060D8 = (*(vu16 *)0x100060D8 & 0xFFDD) | 2; handleNAND.res = 0;
*(vu16 *)0x10006100 &= 0xFFFFu; //SDDATACTL32 handleNAND.initarg = 1;
*(vu16 *)0x100060D8 &= 0xFFDFu; //SDDATACTL handleNAND.clk = 0x20; // 523.655968 KHz
*(vu16 *)0x10006104 = 512; //SDBLKLEN32 handleNAND.devicenumber = 1;
*(vu16 *)0x10006108 = 1; //SDBLKCOUNT32
*(vu16 *)0x100060E0 &= 0xFFFEu; //SDRESET //SD
*(vu16 *)0x100060E0 |= 1u; //SDRESET handleSD.isSDHC = 0;
*(vu16 *)0x10006020 |= TMIO_MASK_ALL; //SDIR_MASK0 handleSD.SDOPT = 0;
*(vu16 *)0x10006022 |= TMIO_MASK_ALL>>16; //SDIR_MASK1 handleSD.res = 0;
*(vu16 *)0x100060FC |= 0xDBu; //SDCTL_RESERVED7 handleSD.initarg = 0;
*(vu16 *)0x100060FE |= 0xDBu; //SDCTL_RESERVED8 handleSD.clk = 0x20; // 523.655968 KHz
*(vu16 *)0x10006002 &= 0xFFFCu; //SDPORTSEL handleSD.devicenumber = 0;
*(vu16 *)0x10006024 = 0x20;
*(vu16 *)0x10006028 = 0x40EE; *(volatile uint16_t*)0x10006100 &= 0xF7FFu; //SDDATACTL32
*(vu16 *)0x10006002 &= 0xFFFCu; ////SDPORTSEL *(volatile uint16_t*)0x10006100 &= 0xEFFFu; //SDDATACTL32
*(vu16 *)0x10006026 = 512; //SDBLKLEN #ifdef DATA32_SUPPORT
*(vu16 *)0x10006008 = 0; //SDSTOP *(volatile uint16_t*)0x10006100 |= 0x402u; //SDDATACTL32
#else
*(volatile uint16_t*)0x10006100 |= 0x402u; //SDDATACTL32
#endif
*(volatile uint16_t*)0x100060D8 = (*(volatile uint16_t*)0x100060D8 & 0xFFDD) | 2;
#ifdef DATA32_SUPPORT
*(volatile uint16_t*)0x10006100 &= 0xFFFFu; //SDDATACTL32
*(volatile uint16_t*)0x100060D8 &= 0xFFDFu; //SDDATACTL
*(volatile uint16_t*)0x10006104 = 512; //SDBLKLEN32
#else
*(volatile uint16_t*)0x10006100 &= 0xFFFDu; //SDDATACTL32
*(volatile uint16_t*)0x100060D8 &= 0xFFDDu; //SDDATACTL
*(volatile uint16_t*)0x10006104 = 0; //SDBLKLEN32
#endif
*(volatile uint16_t*)0x10006108 = 1; //SDBLKCOUNT32
*(volatile uint16_t*)0x100060E0 &= 0xFFFEu; //SDRESET
*(volatile uint16_t*)0x100060E0 |= 1u; //SDRESET
*(volatile uint16_t*)0x10006020 |= TMIO_MASK_ALL; //SDIR_MASK0
*(volatile uint16_t*)0x10006022 |= TMIO_MASK_ALL>>16; //SDIR_MASK1
*(volatile uint16_t*)0x100060FC |= 0xDBu; //SDCTL_RESERVED7
*(volatile uint16_t*)0x100060FE |= 0xDBu; //SDCTL_RESERVED8
*(volatile uint16_t*)0x10006002 &= 0xFFFCu; //SDPORTSEL
#ifdef DATA32_SUPPORT
*(volatile uint16_t*)0x10006024 = 0x20;
*(volatile uint16_t*)0x10006028 = 0x40E9;
#else
*(volatile uint16_t*)0x10006024 = 0x40; //Nintendo sets this to 0x20
*(volatile uint16_t*)0x10006028 = 0x40E9; //Nintendo sets this to 0x40EE
#endif
*(volatile uint16_t*)0x10006002 &= 0xFFFCu; ////SDPORTSEL
*(volatile uint16_t*)0x10006026 = 512; //SDBLKLEN
*(volatile uint16_t*)0x10006008 = 0; //SDSTOP
} }
static int Nand_Init() int Nand_Init()
{ {
//NAND // init the handle
handleNAND.isSDHC = 0; handleNAND.isSDHC = 0;
handleNAND.SDOPT = 0; handleNAND.SDOPT = 0;
handleNAND.res = 0; handleNAND.res = 0;
handleNAND.initarg = 1; handleNAND.initarg = 1;
handleNAND.clk = 0x80; handleNAND.clk = 0x20; // 523.655968 KHz
handleNAND.devicenumber = 1; handleNAND.devicenumber = 1;
inittarget(&handleNAND); // The eMMC is always on. Nothing special to do.
waitcycles(0xF000); set_target(&handleNAND);
sdmmc_send_command(&handleNAND, 0, 0); sdmmc_send_command(&handleNAND,0,0);
do do
{ {
do do
{ {
sdmmc_send_command(&handleNAND, 0x10701, 0x100000); sdmmc_send_command(&handleNAND,0x10701,0x100000);
} } while ( !(handleNAND.error & 1) );
while(!(handleNAND.error & 1)); }
} while((handleNAND.ret[0] & 0x80000000) == 0);
while((handleNAND.ret[0] & 0x80000000) == 0);
sdmmc_send_command(&handleNAND, 0x10602, 0x0); sdmmc_send_command(&handleNAND,0x10602,0x0);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
sdmmc_send_command(&handleNAND, 0x10403, handleNAND.initarg << 0x10); sdmmc_send_command(&handleNAND,0x10403,handleNAND.initarg << 0x10);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
sdmmc_send_command(&handleNAND, 0x10609, handleNAND.initarg << 0x10); sdmmc_send_command(&handleNAND,0x10609,handleNAND.initarg << 0x10);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
handleNAND.total_size = calcSDSize((u8*)&handleNAND.ret[0], 0); handleNAND.total_size = sdmmc_calc_size((uint8_t*)&handleNAND.ret[0],0);
handleNAND.clk = 1; handleNAND.clk = 0; // 33.513982 MHz
setckl(1); setckl(0);
sdmmc_send_command(&handleNAND, 0x10407, handleNAND.initarg << 0x10); sdmmc_send_command(&handleNAND,0x10407,handleNAND.initarg << 0x10);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
handleNAND.SDOPT = 1; handleNAND.SDOPT = 1;
sdmmc_send_command(&handleNAND, 0x10506, 0x3B70100); sdmmc_send_command(&handleNAND,0x10506,0x3B70100);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
sdmmc_send_command(&handleNAND, 0x10506, 0x3B90100); sdmmc_send_command(&handleNAND,0x10506,0x3B90100);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
sdmmc_send_command(&handleNAND, 0x1040D, handleNAND.initarg << 0x10); sdmmc_send_command(&handleNAND,0x1040D,handleNAND.initarg << 0x10);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
sdmmc_send_command(&handleNAND, 0x10410, 0x200); sdmmc_send_command(&handleNAND,0x10410,0x200);
if((handleNAND.error & 0x4)) return -1; if((handleNAND.error & 0x4))return -1;
handleNAND.clk |= 0x200; handleNAND.clk |= 0x200;
inittarget(&handleSD); return 0;
return 0;
} }
static int SD_Init() int SD_Init()
{ {
//SD // init the handle
handleSD.isSDHC = 0; handleSD.isSDHC = 0;
handleSD.SDOPT = 0; handleSD.SDOPT = 0;
handleSD.res = 0; handleSD.res = 0;
handleSD.initarg = 0; handleSD.initarg = 0;
handleSD.clk = 0x80; handleSD.clk = 0x20; // 523.655968 KHz
handleSD.devicenumber = 0; handleSD.devicenumber = 0;
inittarget(&handleSD); // We need to send at least 74 clock pulses.
set_target(&handleSD);
wait(0x1980); // ~75-76 clocks
waitcycles(1u << 22); //Card needs a little bit of time to be detected, it seems FIXME test again to see what a good number is for the delay sdmmc_send_command(&handleSD,0,0);
sdmmc_send_command(&handleSD,0x10408,0x1AA);
uint32_t temp = (handleSD.error & 0x1) << 0x1E;
//If not inserted uint32_t temp2 = 0;
if(!(*((vu16 *)(SDMMC_BASE + REG_SDSTATUS0)) & TMIO_STAT0_SIGSTATE)) return 5;
sdmmc_send_command(&handleSD, 0, 0); do
sdmmc_send_command(&handleSD, 0x10408, 0x1AA); {
u32 temp = (handleSD.error & 0x1) << 0x1E; do
{
sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
sdmmc_send_command(&handleSD,0x10769,0x00FF8000 | temp);
temp2 = 1;
} while ( !(handleSD.error & 1) );
}
while((handleSD.ret[0] & 0x80000000) == 0);
u32 temp2 = 0; if(!((handleSD.ret[0] >> 30) & 1) || !temp)
#ifdef SD_TIMEOUT temp2 = 0;
s32 timeout = SD_TIMEOUT;
#endif // SD_TIMEOUT
do
{
do
{
sdmmc_send_command(&handleSD, 0x10437, handleSD.initarg << 0x10);
sdmmc_send_command(&handleSD, 0x10769, 0x00FF8000 | temp);
temp2 = 1;
#ifdef SD_TIMEOUT
timeout--;
#endif // SD_TIMEOUT
}
while(!(handleSD.error & 1)
#ifdef SD_TIMEOUT
&& timeout > 0
#endif // SD_TIMEOUT
);
}
while((handleSD.ret[0] & 0x80000000) == 0
#ifdef SD_TIMEOUT
&& timeout > 0
#endif // SD_TIMEOUT
);
#ifdef SD_TIMEOUT handleSD.isSDHC = temp2;
if ((handleSD.ret[0] & 0x80000000) == 0) {
return 6;
}
#endif // SD_TIMEOUT
if(!((handleSD.ret[0] >> 30) & 1) || !temp) sdmmc_send_command(&handleSD,0x10602,0);
temp2 = 0; if((handleSD.error & 0x4)) return -1;
handleSD.isSDHC = temp2; sdmmc_send_command(&handleSD,0x10403,0);
if((handleSD.error & 0x4)) return -2;
handleSD.initarg = handleSD.ret[0] >> 0x10;
sdmmc_send_command(&handleSD, 0x10602, 0); sdmmc_send_command(&handleSD,0x10609,handleSD.initarg << 0x10);
if((handleSD.error & 0x4)) return -1; if((handleSD.error & 0x4)) return -3;
sdmmc_send_command(&handleSD, 0x10403, 0); // Command Class 10 support
if((handleSD.error & 0x4)) return -2; const bool cmd6Supported = ((u8*)handleSD.ret)[10] & 0x40;
handleSD.initarg = handleSD.ret[0] >> 0x10; handleSD.total_size = sdmmc_calc_size((uint8_t*)&handleSD.ret[0],-1);
setckl(1);
sdmmc_send_command(&handleSD, 0x10609, handleSD.initarg << 0x10); sdmmc_send_command(&handleSD,0x10507,handleSD.initarg << 0x10);
if((handleSD.error & 0x4)) return -3; if((handleSD.error & 0x4)) return -4;
handleSD.total_size = calcSDSize((u8*)&handleSD.ret[0], -1); // CMD55
handleSD.clk = 1; sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
setckl(1); if(handleSD.error & 0x4) return -5;
sdmmc_send_command(&handleSD, 0x10507, handleSD.initarg << 0x10); // ACMD42 SET_CLR_CARD_DETECT
if((handleSD.error & 0x4)) return -4; sdmmc_send_command(&handleSD,0x1076A,0x0);
if(handleSD.error & 0x4) return -6;
sdmmc_send_command(&handleSD, 0x10437, handleSD.initarg << 0x10); sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
if((handleSD.error & 0x4)) return -5; if((handleSD.error & 0x4)) return -7;
handleSD.SDOPT = 1; handleSD.SDOPT = 1;
sdmmc_send_command(&handleSD, 0x10446, 0x2); sdmmc_send_command(&handleSD,0x10446,0x2);
if((handleSD.error & 0x4)) return -6; if((handleSD.error & 0x4)) return -8;
sdmmc_mask16(REG_SDOPT, 0x8000, 0); // Switch to 4 bit mode.
sdmmc_send_command(&handleSD, 0x1040D, handleSD.initarg << 0x10); // TODO: CMD6 to switch to high speed mode.
if((handleSD.error & 0x4)) return -7; if(cmd6Supported)
{
sdmmc_write16(REG_SDSTOP,0);
sdmmc_write16(REG_SDBLKLEN32,64);
sdmmc_write16(REG_SDBLKLEN,64);
handleSD.rData = NULL;
handleSD.size = 64;
sdmmc_send_command(&handleSD,0x31C06,0x80FFFFF1);
sdmmc_write16(REG_SDBLKLEN,512);
if(handleSD.error & 0x4) return -9;
sdmmc_send_command(&handleSD, 0x10410, 0x200); handleSD.clk = 0x200; // 33.513982 MHz
if((handleSD.error & 0x4)) return -8; setckl(0);
handleSD.clk |= 0x200; }
else handleSD.clk = 0x201; // 16.756991 MHz
return 0; sdmmc_send_command(&handleSD,0x1040D,handleSD.initarg << 0x10);
if((handleSD.error & 0x4)) return -9;
sdmmc_send_command(&handleSD,0x10410,0x200);
if((handleSD.error & 0x4)) return -10;
return 0;
} }
void sdmmc_get_cid(bool isNand, u32 *info) int sdmmc_get_cid(bool isNand, uint32_t *info)
{ {
struct mmcdevice *device = isNand ? &handleNAND : &handleSD; struct mmcdevice *device;
if(isNand)
device = &handleNAND;
else
device = &handleSD;
inittarget(device); set_target(device);
// use cmd7 to put sd card in standby mode
// CMD7
{
sdmmc_send_command(device,0x10507,0);
//if((device->error & 0x4)) return -1;
}
// use cmd7 to put sd card in standby mode // get sd card info
// CMD7 // use cmd10 to read CID
sdmmc_send_command(device, 0x10507, 0); {
sdmmc_send_command(device,0x1060A,device->initarg << 0x10);
//if((device->error & 0x4)) return -2;
// get sd card info for( int i = 0; i < 4; ++i ) {
// use cmd10 to read CID info[i] = device->ret[i];
sdmmc_send_command(device, 0x1060A, device->initarg << 0x10); }
}
for(int i = 0; i < 4; ++i) // put sd card back to transfer mode
info[i] = device->ret[i]; // CMD7
{
sdmmc_send_command(device,0x10507,device->initarg << 0x10);
//if((device->error & 0x4)) return -3;
}
// put sd card back to transfer mode return 0;
// CMD7
sdmmc_send_command(device, 0x10507, device->initarg << 0x10);
} }
u32 sdmmc_sdcard_init() u32 sdmmc_sdcard_init()
{ {
u32 ret = 0; u32 ret = 0;
InitSD();
// SD mount fix
*((vu16*)0x10000020) = 0x340;
// init SDMMC / NAND
sdmmc_init();
if(Nand_Init() != 0) ret &= 1; if(Nand_Init() != 0) ret &= 1;
if(SD_Init() != 0) ret &= 2;
// init SDMMC / SDCARD
u32 timeout = 20; // number of tries (2ms per try)
do {
// if sd card is ready, stop polling
if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_SIGSTATE)
break;
wait_msec(2);
timeout--;
} while(timeout);
if(!timeout || SD_Init() != 0) ret &= 2;
return ret; return ret;
} }

202
arm9/source/nand/sdmmc.h
View File

@ -1,48 +1,74 @@
#pragma once #ifndef __SDMMC_H__
#define __SDMMC_H__
#include "common.h" /*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this file,
* You can obtain one at http://mozilla.org/MPL/2.0/.
*
* Copyright (c) 2014-2015, Normmatt
*
* Alternatively, the contents of this file may be used under the terms
* of the GNU General Public License Version 2, as described below:
*
* This file is free software: you may copy, redistribute and/or modify
* it under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 2 of the License, or (at your
* option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
* Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see http://www.gnu.org/licenses/.
*/
#define SDMMC_BASE 0x10006000 #include <stdint.h>
#include "types.h"
#define REG_SDCMD 0x00 #define SDMMC_BASE 0x10006000
#define REG_SDPORTSEL 0x02
#define REG_SDCMDARG 0x04
#define REG_SDCMDARG0 0x04
#define REG_SDCMDARG1 0x06
#define REG_SDSTOP 0x08
#define REG_SDBLKCOUNT 0x0A
#define REG_SDRESP0 0x0C #define REG_SDCMD 0x00
#define REG_SDRESP1 0x0E #define REG_SDPORTSEL 0x02
#define REG_SDRESP2 0x10 #define REG_SDCMDARG 0x04
#define REG_SDRESP3 0x12 #define REG_SDCMDARG0 0x04
#define REG_SDRESP4 0x14 #define REG_SDCMDARG1 0x06
#define REG_SDRESP5 0x16 #define REG_SDSTOP 0x08
#define REG_SDRESP6 0x18 #define REG_SDBLKCOUNT 0x0a
#define REG_SDRESP7 0x1A
#define REG_SDSTATUS0 0x1C #define REG_SDRESP0 0x0c
#define REG_SDSTATUS1 0x1E #define REG_SDRESP1 0x0e
#define REG_SDRESP2 0x10
#define REG_SDRESP3 0x12
#define REG_SDRESP4 0x14
#define REG_SDRESP5 0x16
#define REG_SDRESP6 0x18
#define REG_SDRESP7 0x1a
#define REG_SDIRMASK0 0x20 #define REG_SDSTATUS0 0x1c
#define REG_SDIRMASK1 0x22 #define REG_SDSTATUS1 0x1e
#define REG_SDCLKCTL 0x24
#define REG_SDBLKLEN 0x26 #define REG_SDIRMASK0 0x20
#define REG_SDOPT 0x28 #define REG_SDIRMASK1 0x22
#define REG_SDFIFO 0x30 #define REG_SDCLKCTL 0x24
#define REG_DATACTL 0xD8 #define REG_SDBLKLEN 0x26
#define REG_SDRESET 0xE0 #define REG_SDOPT 0x28
#define REG_SDPROTECTED 0xF6 //bit 0 determines if sd is protected or not? #define REG_SDFIFO 0x30
#define REG_DATACTL32 0x100 #define REG_DATACTL 0xd8
#define REG_SDBLKLEN32 0x104 #define REG_SDRESET 0xe0
#define REG_SDBLKCOUNT32 0x108 #define REG_SDPROTECTED 0xf6 //bit 0 determines if sd is protected or not?
#define REG_SDFIFO32 0x10C
#define REG_DATACTL32 0x100
#define REG_SDBLKLEN32 0x104
#define REG_SDBLKCOUNT32 0x108
#define REG_SDFIFO32 0x10C
#define REG_CLK_AND_WAIT_CTL 0x138 #define REG_CLK_AND_WAIT_CTL 0x138
#define REG_RESET_SDIO 0x1E0 #define REG_RESET_SDIO 0x1e0
#define TMIO_STAT0_CMDRESPEND 0x0001 #define TMIO_STAT0_CMDRESPEND 0x0001
#define TMIO_STAT0_DATAEND 0x0004 #define TMIO_STAT0_DATAEND 0x0004
@ -66,37 +92,95 @@
#define TMIO_STAT1_CMD_BUSY 0x4000 #define TMIO_STAT1_CMD_BUSY 0x4000
#define TMIO_STAT1_ILL_ACCESS 0x8000 #define TMIO_STAT1_ILL_ACCESS 0x8000
#define TMIO_MASK_ALL 0x837F031D #define TMIO_MASK_ALL 0x837f031d
#define TMIO_MASK_GW (TMIO_STAT1_ILL_ACCESS | TMIO_STAT1_CMDTIMEOUT | TMIO_STAT1_TXUNDERRUN | TMIO_STAT1_RXOVERFLOW | \ #define TMIO_MASK_GW (TMIO_STAT1_ILL_ACCESS | TMIO_STAT1_CMDTIMEOUT | TMIO_STAT1_TXUNDERRUN | TMIO_STAT1_RXOVERFLOW | \
TMIO_STAT1_DATATIMEOUT | TMIO_STAT1_STOPBIT_ERR | TMIO_STAT1_CRCFAIL | TMIO_STAT1_CMD_IDX_ERR) TMIO_STAT1_DATATIMEOUT | TMIO_STAT1_STOPBIT_ERR | TMIO_STAT1_CRCFAIL | TMIO_STAT1_CMD_IDX_ERR)
#define TMIO_MASK_READOP (TMIO_STAT1_RXRDY | TMIO_STAT1_DATAEND) #define TMIO_MASK_READOP (TMIO_STAT1_RXRDY | TMIO_STAT1_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT1_TXRQ | TMIO_STAT1_DATAEND) #define TMIO_MASK_WRITEOP (TMIO_STAT1_TXRQ | TMIO_STAT1_DATAEND)
#define SD_WRITE_PROTECTED (((*((vu16*)(SDMMC_BASE + REG_SDSTATUS0))) & (1 << 7 | 1 << 5)) == (1 << 5)) #define SD_WRITE_PROTECTED (((*((vu16*)(SDMMC_BASE + REG_SDSTATUS0))) & (1 << 7 | 1 << 5)) == (1 << 5))
typedef struct mmcdevice { #ifdef __cplusplus
u8 *rData; extern "C" {
const u8 *tData; #endif
u32 size;
u32 error;
u16 stat0;
u16 stat1;
u32 ret[4];
u32 initarg;
u32 isSDHC;
u32 clk;
u32 SDOPT;
u32 devicenumber;
u32 total_size; //size in sectors of the device
u32 res;
} mmcdevice;
u32 sdmmc_sdcard_init(); typedef struct mmcdevice {
int sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out); uint8_t* rData;
int sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in); const uint8_t* tData;
int sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out); uint32_t size;
int sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in); uint32_t error;
void sdmmc_get_cid(bool isNand, u32 *info); uint16_t stat0;
mmcdevice *getMMCDevice(int drive); uint16_t stat1;
uint32_t ret[4];
uint32_t initarg;
uint32_t isSDHC;
uint32_t clk;
uint32_t SDOPT;
uint32_t devicenumber;
uint32_t total_size; //size in sectors of the device
uint32_t res;
} mmcdevice;
void sdmmc_init();
int sdmmc_sdcard_readsector(uint32_t sector_no, uint8_t *out);
int sdmmc_sdcard_readsectors(uint32_t sector_no, uint32_t numsectors, uint8_t *out);
int sdmmc_sdcard_writesector(uint32_t sector_no, const uint8_t *in);
int sdmmc_sdcard_writesectors(uint32_t sector_no, uint32_t numsectors, const uint8_t *in);
int sdmmc_nand_readsectors(uint32_t sector_no, uint32_t numsectors, uint8_t *out);
int sdmmc_nand_writesectors(uint32_t sector_no, uint32_t numsectors, const uint8_t *in);
int sdmmc_get_cid(bool isNand, uint32_t *info);
mmcdevice *getMMCDevice(int drive);
int Nand_Init();
int SD_Init();
u32 sdmmc_sdcard_init();
#ifdef __cplusplus
};
#endif
//---------------------------------------------------------------------------------
static inline uint16_t sdmmc_read16(uint16_t reg) {
//---------------------------------------------------------------------------------
return *(volatile uint16_t*)(SDMMC_BASE + reg);
}
//---------------------------------------------------------------------------------
static inline void sdmmc_write16(uint16_t reg, uint16_t val) {
//---------------------------------------------------------------------------------
*(volatile uint16_t*)(SDMMC_BASE + reg) = val;
}
//---------------------------------------------------------------------------------
static inline uint32_t sdmmc_read32(uint16_t reg) {
//---------------------------------------------------------------------------------
return *(volatile uint32_t*)(SDMMC_BASE + reg);
}
//---------------------------------------------------------------------------------
static inline void sdmmc_write32(uint16_t reg, uint32_t val) {
//---------------------------------------------------------------------------------
*(volatile uint32_t*)(SDMMC_BASE + reg) = val;
}
//---------------------------------------------------------------------------------
static inline void sdmmc_mask16(uint16_t reg, const uint16_t clear, const uint16_t set) {
//---------------------------------------------------------------------------------
uint16_t val = sdmmc_read16(reg);
val &= ~clear;
val |= set;
sdmmc_write16(reg, val);
}
static inline void setckl(uint32_t data)
{
sdmmc_write16(REG_SDCLKCTL, data & 0xFF);
sdmmc_write16(REG_SDCLKCTL, 1u<<8 | (data & 0x2FF));
}
#endif

2
arm9/source/nand/delay.h → arm9/source/nand/wait.h
View File

@ -2,4 +2,4 @@
#include "common.h" #include "common.h"
void waitcycles(u32 us); void wait(u32 cycles);

11
arm9/source/nand/wait.s Normal file
View File

@ -0,0 +1,11 @@
.text
.arm
.align 4
.global wait
.type wait, %function
wait:
subs r0, r0, #2
nop
bgt wait
bx lr

7
arm9/source/start.s
View File

@ -69,9 +69,10 @@ _start:
mcr p15, 0, r0, c9, c1, 0 @ set the DTCM Region Register mcr p15, 0, r0, c9, c1, 0 @ set the DTCM Region Register
@ Fix SDMC mounting @ Fix SDMC mounting
mov r0, #0x10000000 @ (this is done in sdmmc.c instead)
mov r1, #0x340 @ mov r0, #0x10000000
str r1, [r0, #0x20] @ mov r1, #0x340
@ strh r1, [r0, #0x20]
@ Setup heap @ Setup heap
ldr r0, =fake_heap_start ldr r0, =fake_heap_start