Hardcoded framebuffers

VRAM addresses are in common/vram.h

Now waits for the ARM11 to ack before running

common/vram.h

@@ -0,0 +1,13 @@
+#pragma once
+
+#define TOP_VRAM    (400*240*4)
+#define BOTTOM_VRAM (320*240*4)
+
+#define VRAM_START  (0x18300000)
+#define VRAM_TOP_LA (VRAM_START)
+#define VRAM_TOP_LB (VRAM_TOP_LA + TOP_VRAM)
+#define VRAM_TOP_RA (VRAM_TOP_LB + TOP_VRAM)
+#define VRAM_TOP_RB (VRAM_TOP_RA + TOP_VRAM)
+#define VRAM_BOT_A  (VRAM_TOP_RB + TOP_VRAM)
+#define VRAM_BOT_B  (VRAM_BOT_A  + BOTTOM_VRAM)
+#define VRAM_END    (VRAM_BOT_B  + BOTTOM_VRAM)

screeninit/source/main.c

@@ -7,18 +7,14 @@
 #include <gic.h>
 #include <pxi.h>
 
+#include <vram.h>
+
 // see: https://github.com/AuroraWright/Luma3DS/blob/53209b9be0c264af00fb81b32146d27f0d9498ac/source/screen.h#L32-L34
 #define PDN_GPU_CNT (*(vu8  *)0x10141200)
 #define ARESCREENSINITIALIZED (PDN_GPU_CNT != 1)
 
 #define BASE_BRIGHTNESS (0x1F)
 
-static volatile struct fb {
-     u8 *top_left;
-     u8 *top_right;
-     u8 *bottom;
-} *const fb = (volatile struct fb *)0x23FFFE00;
-
 void screen_init(void)
 {
     char do_disco = !ARESCREENSINITIALIZED;
@@ -55,11 +51,14 @@ void screen_init(void)
     *(vu32 *)0x1040045C = 0x00f00190;
     *(vu32 *)0x10400460 = 0x01c100d1;
     *(vu32 *)0x10400464 = 0x01920002;
-    *(vu32 *)0x10400468 = 0x18300000;
+    *(vu32 *)0x10400468 = VRAM_TOP_LA;
+    *(vu32 *)0x1040046C = VRAM_TOP_LB;
     *(vu32 *)0x10400470 = 0x80341;
     *(vu32 *)0x10400474 = 0x00010501;
     *(vu32 *)0x10400478 = 0;
     *(vu32 *)0x10400490 = 0x000002D0;
+    *(vu32 *)0x10400494 = VRAM_TOP_RA;
+    *(vu32 *)0x10400498 = VRAM_TOP_RB;
     *(vu32 *)0x1040049C = 0x00000000;
 
     //Bottom screen
@@ -85,7 +84,8 @@ void screen_init(void)
     *(vu32 *)0x1040055C = 0x00f00140;
     *(vu32 *)0x10400560 = 0x01c100d1;
     *(vu32 *)0x10400564 = 0x01920052;
-    *(vu32 *)0x10400568 = 0x18346500;
+    *(vu32 *)0x10400568 = VRAM_BOT_A;
+    *(vu32 *)0x1040056C = VRAM_BOT_B;
     *(vu32 *)0x10400570 = 0x80301;
     *(vu32 *)0x10400574 = 0x00010501;
     *(vu32 *)0x10400578 = 0;
@@ -99,30 +99,18 @@ void screen_init(void)
         }
     }
 
-    //Set CakeBrah framebuffers
-    fb->top_left = (u8 *)0x18300000;
-    fb->top_right = (u8 *)0x18300000;
-    fb->bottom = (u8 *)0x18346500;
-
-    *(vu32 *)0x10400468 = (u32)fb->top_left;
-    *(vu32 *)0x1040046c = (u32)fb->top_left;
-    *(vu32 *)0x10400494 = (u32)fb->top_right;
-    *(vu32 *)0x10400498 = (u32)fb->top_right;
-    *(vu32 *)0x10400568 = (u32)fb->bottom;
-    *(vu32 *)0x1040056c = (u32)fb->bottom;
-
     vu32 *REGs_PSC0 = (vu32 *)0x10400010,
          *REGs_PSC1 = (vu32 *)0x10400020;
 
-    REGs_PSC0[0] = (u32)fb->top_left >> 3; //Start address
+    REGs_PSC0[0] = VRAM_START >> 3;
-    REGs_PSC0[1] = (u32)(fb->top_left + 0x46500) >> 3; //End address
+    REGs_PSC0[1] = ((VRAM_START + VRAM_END) / 2) >> 3;
-    REGs_PSC0[2] = 0; //Fill value
+    REGs_PSC0[2] = 0;
-    REGs_PSC0[3] = (2 << 8) | 1; //32-bit pattern; start
+    REGs_PSC0[3] = (2 << 8) | 1;
 
-    REGs_PSC1[0] = (u32)fb->bottom >> 3; //Start address
+    REGs_PSC1[0] = ((VRAM_START + VRAM_END) / 2) >> 3;
-    REGs_PSC1[1] = (u32)(fb->bottom + 0x38400) >> 3; //End address
+    REGs_PSC1[1] = VRAM_END >> 3;
-    REGs_PSC1[2] = 0; //Fill value
+    REGs_PSC1[2] = 0;
-    REGs_PSC1[3] = (2 << 8) | 1; //32-bit pattern; start
+    REGs_PSC1[3] = (2 << 8) | 1;
 
     while(!((REGs_PSC0[3] & 2) && (REGs_PSC1[3] & 2)));
     return;
@@ -169,5 +157,7 @@ void main(void)
 
     CPU_DisableIRQ();
     PXI_DisableIRQ();
+    PXI_Reset();
+    GIC_Reset();
     ((void (*)())(entry))();
 }

source/common/ui.h

@@ -4,8 +4,10 @@
 
 #pragma once
 
+#include <vram.h>
 #include "common.h"
 
+
 #define BYTES_PER_PIXEL 3
 #define SCREEN_HEIGHT 240
 #define SCREEN_WIDTH_TOP 400
@@ -52,8 +54,8 @@
 #define COLOR_STD_BG        COLOR_BLACK
 #define COLOR_STD_FONT      COLOR_WHITE
 
-#define TOP_SCREEN          ((u8*)(*(u32*)0x23FFFE00))
+#define TOP_SCREEN          ((u8*)VRAM_TOP_LA)
-#define BOT_SCREEN          ((u8*)(*(u32*)0x23FFFE08))
+#define BOT_SCREEN          ((u8*)VRAM_BOT_A)
 
 #ifdef SWITCH_SCREENS
 #define MAIN_SCREEN         TOP_SCREEN

source/start.s

@@ -116,6 +116,13 @@ _start_gm:
         strlt r3, [r2], #4
         blt .LXRQ_Install
 
+    @ Wait for the ARM11 to do its thing
+    mov r0, #0x20000000
+    .LWaitMPC:
+        ldr r1, [r0, #-4]
+        cmp r1, #0
+        bne .LWaitMPC
+
     @ Enable caches / select low exception vectors
     ldr r1, =(CR_ALT_VECTORS | CR_DISABLE_TBIT)
     ldr r2, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \

source/system/bootfirm.s

@@ -2,14 +2,19 @@
 .arm
 .align 4
 
-.equ ARG_MAGIC, 0xBEEF
+#include <arm.h>
+#include <vram.h>
+
+.equ ARG_MAGIC, 0x0000BEEF
 .equ MPCORE_LD, 0x27FFFB00
 .equ STUB_LOC,  0x27FFFC00
-.equ FBPTR_LOC, 0x23FFFE00
+.equ ARGV_LOC,  0x27FFFE00
-.equ ARGV_LOC,  0x23FFFE20
+.equ FBPTR_LOC, 0x27FFFE08
+.equ PATH_LOC,  0x27FFFF00
 
 .cpu mpcore
 MPCore_stub:
+    cpsid aif, #(SR_SVC_MODE)
     mov r0, #0x20000000
     mov r1, #0
     str r1, [r0, #-4]
@@ -59,7 +64,7 @@ BootFirm_stub:
         @ CPSR:
         @ ARM, Supervisor, IRQ/FIQs disabled
         @ Flags are undefined
-        msr cpsr_c, #0xD3
+        msr cpsr_c, #(SR_SVC_MODE | SR_IRQ | SR_FIQ)
 
         @ CP15:
         @ MPU and Caches are off
@@ -73,7 +78,7 @@ BootFirm_stub:
         blx r5
 
         @ Registers:
-        @ R0 = 0x00000002
+        @ R0 = 0x1 or 0x2
         @ R1 = 0x23FFFE10
         @ R2 = 0x0000BEEF
         @ R3-R14 are undefined
@@ -88,9 +93,8 @@ BootFirm_stub:
 
 
     @ Setup argv
-    str r9, [r1, #0x00] @ FIRM path / argv[0]
-
     ldrne r3, =FBPTR_LOC
+    str r9,   [r1, #0x00] @ FIRM path / argv[0]
     strne r3, [r1, #0x04] @ Framebuffers / argv[1]
 
     @ Fetch FIRM entrypoints
@@ -114,9 +118,23 @@ BootFirm_stub_end:
 .type BootFirm, %function
 BootFirm:
     mov r10, r0
+    mov r11, r1
+
+    @ Setup the framebuffer struct
+    ldr r0, =FBPTR_LOC
+    ldr r1, =VRAM_TOP_LA
+    ldr r2, =VRAM_TOP_RA
+    ldr r3, =VRAM_BOT_A
+    stmia r0!, {r1,r2,r3}
+
+    ldr r1, =VRAM_TOP_LB
+    ldr r2, =VRAM_TOP_RB
+    ldr r3, =VRAM_BOT_B
+    stmia r0!, {r1,r2,r3}
 
     @ Copy the FIRM path somewhere safe
-    ldr r0, =(ARGV_LOC+8)
+    ldr r0, =PATH_LOC
+    mov r1, r11
     mov r11, r0
     blx strcpy