Replaced bootstrap .ld and .s files

Using CakesFW ones now!

bootstrap.ld

@@ -1,130 +1,12 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
 ENTRY(_start)
-
-MEMORY
-  {
-  ram : ORIGIN = 0x23F00000, LENGTH = 128K
-  }
-
 SECTIONS
 {
-	.init	:
+    . = 0x23F00000;
-	{
+    .text.start : { *(.text.start) }
-		__text_start = . ;
+    .text : { *(.text) }
-		KEEP (*(.init))
+    .data : { *(.data) }
-		. = ALIGN(4);  /* REQUIRED. LD is flaky without it. */
+    .bss : { *(.bss COMMON) }
-		} >ram = 0xff
+    .rodata : { *(.rodata) }
-	.plt : { *(.plt) } >ram = 0xff
+    . = ALIGN(4);
-
+    __end__ = ABSOLUTE(.);
-	.text :   /* ALIGN (4): */
+}
-	{
-		*(.text .stub .text.* .gnu.linkonce.t.*)
-		KEEP (*(.text.*personality*))
-		/* .gnu.warning sections are handled specially by elf32.em.  */
-		*(.gnu.warning)
-		*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
-		. = ALIGN(4);  /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-
-	.fini           :
-	{
-		KEEP (*(.fini))
-	} >ram =0xff
-
-	__text_end = . ;
-
-	.rodata :
-	{
-		*(.rodata)
-		*all.rodata*(*)
-		*(.roda)
-		*(.rodata.*)
-		*(.gnu.linkonce.r*)
-		SORT(CONSTRUCTORS)
-		. = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-
-	.ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ram
-	__exidx_start = .;
-	.ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >ram
-	__exidx_end = .;
-
-/* Ensure the __preinit_array_start label is properly aligned.  We
-   could instead move the label definition inside the section, but
-   the linker would then create the section even if it turns out to
-   be empty, which isn't pretty.  */
-	. = ALIGN(32 / 8);
-	PROVIDE (__preinit_array_start = .);
-	.preinit_array     : { KEEP (*(.preinit_array)) } >ram = 0xff
-	PROVIDE (__preinit_array_end = .);
-	PROVIDE (__init_array_start = .);
-	.init_array     : { KEEP (*(.init_array)) } >ram = 0xff
-	PROVIDE (__init_array_end = .);
-	PROVIDE (__fini_array_start = .);
-	.fini_array     : { KEEP (*(.fini_array)) } >ram = 0xff
-	PROVIDE (__fini_array_end = .);
-
-	.ctors :
-	{
-	/* gcc uses crtbegin.o to find the start of the constructors, so
-		we make sure it is first.  Because this is a wildcard, it
-		doesn't matter if the user does not actually link against
-		crtbegin.o; the linker won't look for a file to match a
-		wildcard.  The wildcard also means that it doesn't matter which
-		directory crtbegin.o is in.  */
-		KEEP (*crtbegin.o(.ctors))
-		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-		KEEP (*(SORT(.ctors.*)))
-		KEEP (*(.ctors))
-		. = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-
-	.dtors :
-	{
-		KEEP (*crtbegin.o(.dtors))
-		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-		KEEP (*(SORT(.dtors.*)))
-		KEEP (*(.dtors))
-		. = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-
-	.eh_frame :
-	{
-		KEEP (*(.eh_frame))
-		. = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-
-	.gcc_except_table :
-	{
-		*(.gcc_except_table)
-		. = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-	} >ram = 0xff
-	.jcr            : { KEEP (*(.jcr)) } >ram = 0
-	.got            : { *(.got.plt) *(.got) } >ram = 0
-
-	.data ALIGN(4) : 	{
-		__data_start = ABSOLUTE(.);
-		*(.data)
-		*(.data.*)
-		*(.gnu.linkonce.d*)
-		CONSTRUCTORS
-		. = ALIGN(4);
-		__data_end = ABSOLUTE(.) ;
-	} >ram = 0xff
-
-	.bss ALIGN(4) :
-	{
-		__bss_start = ABSOLUTE(.);
-		__bss_start__ = ABSOLUTE(.);
-		*(.dynbss)
-		*(.gnu.linkonce.b*)
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);    /* REQUIRED. LD is flaky without it. */
-		__bss_end__ = ABSOLUTE(.);
-		__end__ = ABSOLUTE(.);
-	} >ram
-
-	.stack 0x80000 : { _stack = .; *(.stack) }
-}

source/abstraction/bs-start.s

@@ -1,20 +1,18 @@
 #ifdef EXEC_BOOTSTRAP
 
-.section ".init"
+.section .text.start
-.global _start
-.extern main
 .align 4
-.arm
+.global _start
 _start:
     @ Change the stack pointer
     mov sp, #0x27000000
-    
-    @ Give read/write access to all the memory regions
-    ldr r0, =0x33333333
-    mcr p15, 0, r0, c5, c0, 2 @ write data access
-    mcr p15, 0, r0, c5, c0, 3 @ write instruction access
 
-    @ Set MPU permissions and cache settings
+    @ Give read/write access to all the memory regions
+    ldr r5, =0x33333333
+    mcr p15, 0, r5, c5, c0, 2 @ write data access
+    mcr p15, 0, r5, c5, c0, 3 @ write instruction access
+
+    @ Sets MPU permissions and cache settings
     ldr r0, =0xFFFF001D	@ ffff0000 32k
     ldr r1, =0x01FF801D	@ 01ff8000 32k
     ldr r2, =0x08000027	@ 08000000 1M
@@ -23,6 +21,9 @@ _start:
     ldr r5, =0x20000035	@ 20000000 128M
     ldr r6, =0x1FF00027	@ 1FF00000 1M
     ldr r7, =0x1800002D	@ 18000000 8M
+    mov r10, #0x25
+    mov r11, #0x25
+    mov r12, #0x25
     mcr p15, 0, r0, c6, c0, 0
     mcr p15, 0, r1, c6, c1, 0
     mcr p15, 0, r2, c6, c2, 0
@@ -31,24 +32,28 @@ _start:
     mcr p15, 0, r5, c6, c5, 0
     mcr p15, 0, r6, c6, c6, 0
     mcr p15, 0, r7, c6, c7, 0
-    mov r0, #0x25
+    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r0, c2, c0, 0  @ data cacheable
+    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r0, c2, c0, 1  @ instruction cacheable
+    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
-    mcr p15, 0, r0, c3, c0, 0  @ data bufferable
+
- 
     @ Enable caches
-    mrc p15, 0, r0, c1, c0, 0  @ read control register
+    mrc p15, 0, r4, c1, c0, 0  @ read control register
-    orr r0, r0, #(1<<18)       @ - itcm enable
+    orr r4, r4, #(1<<18)       @ - itcm enable
-    orr r0, r0, #(1<<12)       @ - instruction cache enable
+    orr r4, r4, #(1<<12)       @ - instruction cache enable
-    orr r0, r0, #(1<<2)        @ - data cache enable
+    orr r4, r4, #(1<<2)        @ - data cache enable
-    orr r0, r0, #(1<<0)        @ - mpu enable
+    orr r4, r4, #(1<<0)        @ - mpu enable
-    mcr p15, 0, r0, c1, c0, 0  @ write control register
+    mcr p15, 0, r4, c1, c0, 0  @ write control register
 
     @ Flush caches
-    mov r0, #0
+    mov r5, #0
-    mcr p15, 0, r0, c7, c5, 0  @ flush I-cache
+    mcr p15, 0, r5, c7, c5, 0  @ flush I-cache
-    mcr p15, 0, r0, c7, c6, 0  @ flush D-cache
+    mcr p15, 0, r5, c7, c6, 0  @ flush D-cache
-    mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+    mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
+
+    @ Fixes mounting of SDMC
+	ldr r0, =0x10000020
+	mov r1, #0x340
+	str r1, [r0]
 
     bl main