mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 05:32:47 +00:00
- enable the VFP on the ARM11
- stopped using the ITCM as the interrupt vector table - removed dead Thumb code handler in interrupt handling - added basic memory protection flags
This commit is contained in:
Wolfvak
d0k3
parent
8b098fa91a
commit
ca7944ce04
@ -5,7 +5,7 @@ TARGET := $(shell basename $(CURDIR))
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SOURCE := source
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BUILD := build
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SUBARCH := -D$(PROCESSOR) -mcpu=mpcore -mtune=mpcore -mfloat-abi=soft -marm
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SUBARCH := -D$(PROCESSOR) -marm -march=armv6k -mtune=mpcore -mfloat-abi=hard -mfpu=vfpv2 -mtp=soft
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INCDIRS := source
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INCLUDE := $(foreach dir,$(INCDIRS),-I"$(shell pwd)/$(dir)")
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@ -26,6 +26,7 @@
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.global __boot
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__boot:
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cpsid aif, #SR_SVC_MODE
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clrex
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@ Writeback and invalidate all DCache
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@ Invalidate all caches
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@ -44,6 +45,18 @@ __boot:
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mcr p15, 0, r1, c1, c0, 1
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mcr p15, 0, r2, c1, c0, 2
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@ VFPv2 init
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@ https://github.com/derrekr/fastboot3DS/blob/f63c967369451b1fd0078e649cf0010fe10a62fd/source/arm11/start.s#L195
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mov r0, #0
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mov r1, #0xF00000 @ Give full access to cp10/11 in user and privileged mode
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mov r2, #0x40000000 @ Clear exception bits and enable VFP11
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mov r3, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode
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mcr p15, 0, r1, c1, c0, 2 @ Write Coprocessor Access Control Register
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mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer
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fmxr fpexc, r2 @ Write Floating-point exception register
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fmxr fpscr, r3 @ Write Floating-Point Status and Control Register
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@ Get CPU ID
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mrc p15, 0, r12, c0, c0, 5
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ands r12, r12, #3
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@ -5,7 +5,7 @@ TARGET := $(shell basename $(CURDIR))
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SOURCE := source
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BUILD := build
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SUBARCH := -D$(PROCESSOR) -mcpu=arm946e-s -mtune=arm946e-s -mfloat-abi=soft -mno-thumb-interwork -marm
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SUBARCH := -D$(PROCESSOR) -marm -march=armv5te -mtune=arm946e-s -mfloat-abi=soft -mno-thumb-interwork
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INCDIRS := source source/common source/filesys source/crypto source/fatfs source/nand source/virtual source/game source/gamecart source/lodepng source/qrcodegen source/system source/utils
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INCLUDE := $(foreach dir,$(INCDIRS),-I"$(shell pwd)/$(dir)")
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47
arm9/link.ld
47
arm9/link.ld
@ -2,19 +2,46 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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MEMORY
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{
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AHBWRAM (RWX) : ORIGIN = 0x08006000, LENGTH = 512K
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VECTORS (RX) : ORIGIN = 0x08000000, LENGTH = 64
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}
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SECTIONS
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{
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. = 0x08006000;
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__start__ = ABSOLUTE(.);
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.text.start : ALIGN(4) { *(.text.start) }
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.text : ALIGN(4) { *(.text*) }
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.rodata : ALIGN(4) { *(.rodata*) }
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.data : ALIGN(4) { *(.data*) }
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.bss : ALIGN(4) { __bss_start = .; *(.bss* COMMON); __bss_end = .;}
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.vectors : ALIGN(4) {
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__vectors_lma = LOADADDR(.vectors);
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__vectors_vma = ABSOLUTE(.);
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KEEP(*(.vectors));
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. = ALIGN(4);
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__vectors_len = ABSOLUTE(.) - __vectors_vma;
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} >VECTORS AT>AHBWRAM
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.text : ALIGN(4) {
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__text_s = ABSOLUTE(.);
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*(.text.start);
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*(.text*);
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. = ALIGN(4);
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__text_e = ABSOLUTE(.);
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} >AHBWRAM
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.rodata : ALIGN(4) {
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*(.rodata*);
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. = ALIGN(4);
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} >AHBWRAM
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(4);
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} >AHBWRAM
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.bss : ALIGN(4) {
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__bss_start = .;
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*(.bss*);
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. = ALIGN(4);
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__bss_end = .;
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} >AHBWRAM
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__end__ = ABSOLUTE(.);
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__code_size__ = __end__ - __start__;
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}
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@ -32,18 +32,18 @@ _start:
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ldr r0, =BRF_INVALIDATE_ICACHE
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blx r0 @ Invalidate Instruction Cache
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@ Disable caches / DTCM / MPU
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ldr r1, =(CR_MPU | CR_CACHES | CR_DTCM | CR_TCM_LOAD)
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ldr r2, =(CR_ITCM)
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@ Disable caches / TCMs / MPU
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ldr r1, =(CR_MPU | CR_CACHES | CR_DTCM | CR_ITCM | CR_TCM_LOAD)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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mcr p15, 0, r0, c1, c0, 0
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@ Give full access to defined memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set access permissions
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ldr r0, =0x11111115 @ RO data access for BootROM, RW otherwise
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ldr r1, =0x00505005 @ Can only execute code from ARM9 RAM, FCRAM and BootROM
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mcr p15, 0, r0, c5, c0, 2
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mcr p15, 0, r1, c5, c0, 3
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@ Set MPU regions and cache settings
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ldr r0, =__mpu_regions
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@ -64,15 +64,12 @@ _start:
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable
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@ Enable DTCM
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@ Configure TCMs
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ldr r0, =0x3000800A
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mcr p15, 0, r0, c9, c1, 0 @ set the DTCM Region Register
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ldr r1, =0x00000024
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mcr p15, 0, r0, c9, c1, 0 @ DTCM
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mcr p15, 0, r1, c9, c1, 1 @ ITCM
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@ Fix SDMC mounting
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@ (this is done in sdmmc.c instead)
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@ mov r0, #0x10000000
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@ mov r1, #0x340
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@ strh r1, [r0, #0x20]
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@ Setup heap
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ldr r0, =fake_heap_start
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@ -84,18 +81,18 @@ _start:
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str r1, [r0]
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@ Install exception handlers
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ldr r0, =XRQ_Start
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ldr r1, =XRQ_End
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ldr r2, =0x00000000
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ldr r0, =__vectors_lma
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ldr r1, =__vectors_len
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ldr r2, =XRQ_Start
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add r1, r0, r1
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.LXRQ_Install:
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cmp r0, r1
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ldrlo r3, [r0], #4
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strlo r3, [r2], #4
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blo .LXRQ_Install
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@ Enable caches / DTCM / select low exception vectors
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ldr r1, =(CR_ALT_VECTORS | CR_V4TLD)
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ldr r2, =(CR_MPU | CR_CACHES | CR_DTCM)
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@ Enable caches / TCMs / select high exception vectors
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ldr r2, =(CR_MPU | CR_CACHES | CR_ITCM | CR_DTCM | CR_ALT_VECTORS)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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@ -162,7 +159,7 @@ _start:
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__mpu_regions:
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.word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected)
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.word 0x3000801B @ 30008000 16k | dtcm
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.word 0x00000035 @ 00000000 128M | itcm (+ mirrors)
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.word 0x01FF8035 @ 01FF8000 32k | itcm (+ mirrors)
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.word 0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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.word 0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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.word 0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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@ -15,23 +15,45 @@
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#include <arm.h>
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#define PC_DUMPRAD (0x30)
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#define SP_DUMPLEN (0x60)
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#define PC_DUMPRAD (0x40)
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#define SP_DUMPLEN (0x30)
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extern u32 __text_s, __text_e;
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static bool sp_dumpable(u32 sp, u32 *sp_lower, u32 *sp_upper)
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{
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if ((sp >= __STACK_TOP) || (sp < (__STACK_TOP - __STACK_LEN)))
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return false;
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*sp_lower = sp;
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*sp_upper = min(sp + SP_DUMPLEN, __STACK_TOP);
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return true;
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}
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static bool pc_dumpable(u32 pc, u32 *pc_lower, u32 *pc_upper)
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{
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u32 code_start = (u32)(&__text_s), code_end = (u32)(&__text_e);
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if ((pc >= code_end) || (pc < code_start))
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return false;
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*pc_lower = max(pc - PC_DUMPRAD, code_start);
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*pc_upper = min(pc + PC_DUMPRAD, code_end);
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return true;
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}
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#define XRQ_DUMPDATAFUNC(type, size) \
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int XRQ_DumpData_##type(char *b, u32 s, u32 e) \
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static unsigned XRQ_DumpData_##type(char *b, u32 s, u32 e) \
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{ \
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char *c = b; \
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while(s<e) { \
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b+=sprintf(b, "%08lX: ",s); \
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type *dl = (type*)s; \
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for (u32 i=0; i<(16/((size)/2)); i++) { \
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for (u32 i = 0; i < (16 / sizeof(type)); i++) { \
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b+=sprintf(b, "%0" #size "lX ", (u32)dl[i]); \
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} \
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b+=sprintf(b, "\n"); \
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s+=16; \
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} \
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return (int)(b-c); \
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return (unsigned)(b-c); \
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}
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XRQ_DUMPDATAFUNC(u8, 2)
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XRQ_DUMPDATAFUNC(u16, 4)
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@ -46,7 +68,7 @@ const char *XRQ_Name[] = {
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void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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{
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u32 sp, st, pc;
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u32 sp, sp_lower, sp_upper, pc, pc_lower, pc_upper;
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char dumpstr[2048], *wstr = dumpstr;
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DsTime dstime;
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@ -75,25 +97,26 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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ClearScreen(MAIN_SCREEN, COLOR_STD_BG);
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DrawStringF(MAIN_SCREEN, draw_x, draw_y, COLOR_STD_FONT, COLOR_STD_BG, dumpstr);
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/* Dump STACK */
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sp = regs[13] & ~0xF;
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st = __STACK_TOP;
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wstr += sprintf(wstr, "Stack dump:\n");
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wstr += XRQ_DumpData_u8(wstr, sp, min(sp+SP_DUMPLEN, st));
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if (sp_dumpable(sp, &sp_lower, &sp_upper)) {
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wstr += sprintf(wstr, "Stack:\n");
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wstr += XRQ_DumpData_u8(wstr, sp_lower, sp_upper);
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wstr += sprintf(wstr, "\n");
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}
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/* Dump TEXT */
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/* Dump CODE */
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pc = regs[15] & ~0xF;
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wstr += sprintf(wstr, "Code dump:\n");
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if (regs[16] & SR_THUMB) {
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if (pc_dumpable(pc, &pc_lower, &pc_upper)) {
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wstr += sprintf(wstr, "Code:\n");
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wstr += XRQ_DumpData_u32(wstr, pc_lower, pc_upper);
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/*if (regs[16] & SR_THUMB) { // no need to take Thumb code into account
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wstr += XRQ_DumpData_u16(wstr, pc-PC_DUMPRAD, pc+PC_DUMPRAD);
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} else {
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wstr += XRQ_DumpData_u32(wstr, pc-PC_DUMPRAD, pc+PC_DUMPRAD);
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}*/
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}
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/* Draw QR Code */
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u8 qrcode[qrcodegen_BUFFER_LEN_MAX];
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u8 temp[qrcodegen_BUFFER_LEN_MAX];
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@ -3,125 +3,95 @@
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Read LICENSE for more details
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*/
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.section .text.xrqh
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.arm
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#include <arm.h>
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#include <brf.h>
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#include "memmap.h"
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.macro XRQ_FATAL id=0
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ldr sp, =__STACK_ABT_TOP
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sub sp, sp, #(18*4) @ Reserve space for registers
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stmia sp, {r0-r12}
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mov r11, #\id
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b XRQ_MainHandler
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.macro TRAP_ENTRY xrq_id
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msr cpsr_f, #(\xrq_id << 29) @ preserve xrq id (idea grabbed from fb3ds)
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.endm
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.section .vectors, "ax"
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.global XRQ_Start
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XRQ_Start:
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XRQ_Vectors:
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b XRQ_Reset
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b XRQ_Undefined
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b XRQ_SWI
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b XRQ_PAbort
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b XRQ_DAbort
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b . @ Reserved exception vector
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subs pc, lr, #4 @ IRQs are unhandled
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b . @ FIQs are unused (except for debug?)
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ldr pc, IRQ_Vector
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IRQ_Vector: .word IRQ_Handler
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ldr pc, FIQ_Vector
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FIQ_Vector: .word FIQ_Handler
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ldr pc, SVC_Vector
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SVC_Vector: .word SVC_Handler
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ldr pc, UND_Vector
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UND_Vector: .word UND_Handler
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ldr pc, PABT_Vector
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PABT_Vector: .word PABT_Handler
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ldr pc, DABT_Vector
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DABT_Vector: .word DABT_Handler
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.global XRQ_End
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XRQ_End:
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XRQ_Reset:
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msr cpsr_c, #(SR_ABT_MODE | SR_NOINT)
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XRQ_FATAL 0
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XRQ_Undefined:
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XRQ_FATAL 1
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.section .text.xrqs
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IRQ_Handler:
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TRAP_ENTRY 6
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b XRQ_Fatal
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XRQ_SWI:
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XRQ_FATAL 2
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FIQ_Handler:
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TRAP_ENTRY 7
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b XRQ_Fatal
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XRQ_PAbort:
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XRQ_FATAL 3
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SVC_Handler:
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TRAP_ENTRY 2
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b XRQ_Fatal
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XRQ_DAbort:
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XRQ_FATAL 4
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UND_Handler:
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TRAP_ENTRY 1
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b XRQ_Fatal
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@ r11 = exception number
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XRQ_MainHandler:
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mrs r10, cpsr
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mrs r9, spsr
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mov r8, lr
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PABT_Handler:
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TRAP_ENTRY 3
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b XRQ_Fatal
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@ Disable mpu / caches
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ldr r4, =BRF_WB_INV_DCACHE
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ldr r5, =BRF_INVALIDATE_ICACHE
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ldr r6, =BRF_RESETCP15
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blx r4
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blx r5
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blx r6
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DABT_Handler:
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sub lr, lr, #4 @ R14_abt = PC + 8, so it needs a small additional fixup
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TRAP_ENTRY 4
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@b XRQ_Fatal
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@ Retrieve banked registers
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ands r0, r9, #(SR_PMODE_MASK & (0x0F))
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orreq r0, #(SR_SYS_MODE)
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orr r0, #(0x10 | SR_NOINT)
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XRQ_Fatal:
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sub lr, lr, #4 @ PC exception fixup
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msr cpsr_c, r0 @ Switch to previous mode
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mov r0, sp
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mov r1, lr
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msr cpsr_c, r10 @ Return to abort
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ldr sp, =(__STACK_ABT_TOP - 18*4) @ Set up abort stack, 8 byte aligned
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stmia sp, {r0-r7} @ Preserve non-banked GPRs
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add r2, sp, #(13*4)
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stmia r2, {r0, r1, r8, r9}
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mrs r1, cpsr
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orr r0, r1, #SR_NOINT
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msr cpsr_c, r0 @ Disable interrupts
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@ Give read/write access to all the memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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lsr r0, r1, #29 @ Retrieve exception source
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@ Sets MPU regions and cache settings
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adr r0, __abt_mpu_regions
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ldmia r0, {r1-r8}
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mov r0, #0b00110010 @ bootrom, arm9 mem and fcram are cacheable/bufferable
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mcr p15, 0, r1, c6, c0, 0
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mcr p15, 0, r2, c6, c1, 0
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mcr p15, 0, r3, c6, c2, 0
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mcr p15, 0, r4, c6, c3, 0
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mcr p15, 0, r5, c6, c4, 0
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mcr p15, 0, r6, c6, c5, 0
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mcr p15, 0, r7, c6, c6, 0
|
||||
mcr p15, 0, r8, c6, c7, 0
|
||||
mcr p15, 0, r0, c3, c0, 0 @ Write bufferable 0, 2, 5
|
||||
mcr p15, 0, r0, c2, c0, 0 @ Data cacheable 0, 2, 5
|
||||
mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable 0, 2, 5
|
||||
mrs r2, spsr
|
||||
str lr, [sp, #15*4]
|
||||
str r2, [sp, #16*4] @ Preserve exception PC and CPSR
|
||||
|
||||
@ Enable mpu/caches
|
||||
ldr r1, =(CR_MPU | CR_CACHES | CR_DTCM)
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, r1
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
ands r2, r2, #SR_PMODE_MASK
|
||||
orreq r2, r2, #SR_SYS_MODE @ Force a switch to system mode if
|
||||
@ the exception happened in user mode
|
||||
orr r2, r2, #(0x10 | SR_NOINT) @ With interrupts disabled
|
||||
|
||||
add r3, sp, #8*4
|
||||
msr cpsr_c, r2
|
||||
nop
|
||||
nop
|
||||
stmia r3, {r8-r14} @ Preserve banked GPRs (R8-R12, SP_xrq, LR_xrq)
|
||||
nop
|
||||
nop
|
||||
msr cpsr_c, r1
|
||||
|
||||
ldr r2, =XRQ_DumpRegisters @ void XRQ_DumpRegisters(u32 xrq_id, u32 *regs)
|
||||
mov r1, sp
|
||||
mov r0, r11
|
||||
blx r2
|
||||
bl XRQ_DumpRegisters @ XRQ_DumpRegisters(exception_number, saved_regs);
|
||||
|
||||
msr cpsr, #(SR_SVC_MODE | SR_NOINT)
|
||||
mov r0, #0
|
||||
1:
|
||||
mcr p15, 0, r0, c7, c0, 4
|
||||
b 1b
|
||||
|
||||
.pool
|
||||
|
||||
__abt_mpu_regions:
|
||||
.word 0x0000003F @ 00000000 4G | background region (includes IO regs)
|
||||
.word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected)
|
||||
.word 0x3000801B @ 30008000 16k | dtcm
|
||||
.word 0x00000035 @ 00000000 128M | itcm
|
||||
.word 0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
|
||||
.word 0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
|
||||
.word 0x1FF00027 @ 1FF00000 1M | dsp / axi wram
|
||||
.word 0x1800002D @ 18000000 8M | vram (+ 2MB)
|
||||
|
||||
.global XRQ_End
|
||||
XRQ_End:
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user