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https://github.com/d0k3/GodMode9.git
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128 lines
3.0 KiB
ArmAsm
128 lines
3.0 KiB
ArmAsm
/*
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Written by Wolfvak, specially sublicensed under the GPLv2
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Read LICENSE for more details
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*/
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.section .text.xrqh
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.arm
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#include <arm.h>
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#include <brf.h>
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#include "memmap.h"
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.macro XRQ_FATAL id=0
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ldr sp, =__STACK_ABT_TOP
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sub sp, sp, #(18*4) @ Reserve space for registers
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stmia sp, {r0-r12}
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mov r11, #\id
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b XRQ_MainHandler
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.endm
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.global XRQ_Start
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XRQ_Start:
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XRQ_Vectors:
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b XRQ_Reset
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b XRQ_Undefined
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b XRQ_SWI
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b XRQ_PAbort
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b XRQ_DAbort
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b . @ Reserved exception vector
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subs pc, lr, #4 @ IRQs are unhandled
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b . @ FIQs are unused (except for debug?)
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XRQ_Reset:
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msr cpsr_c, #(SR_ABT_MODE | SR_IRQ | SR_FIQ)
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XRQ_FATAL 0
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XRQ_Undefined:
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XRQ_FATAL 1
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XRQ_SWI:
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XRQ_FATAL 2
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XRQ_PAbort:
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XRQ_FATAL 3
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XRQ_DAbort:
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XRQ_FATAL 4
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@ r11 = exception number
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XRQ_MainHandler:
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mrs r10, cpsr
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mrs r9, spsr
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mov r8, lr
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@ Disable mpu / caches
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ldr r4, =BRF_WB_INV_DCACHE
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ldr r5, =BRF_INVALIDATE_ICACHE
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ldr r6, =BRF_RESETCP15
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blx r4
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blx r5
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blx r6
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@ Retrieve banked registers
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ands r0, r9, #(SR_PMODE_MASK & (0x0F))
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orreq r0, #(SR_SYS_MODE)
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orr r0, #(0x10 | SR_IRQ | SR_FIQ)
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msr cpsr_c, r0 @ Switch to previous mode
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mov r0, sp
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mov r1, lr
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msr cpsr_c, r10 @ Return to abort
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add r2, sp, #(13*4)
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stmia r2, {r0,r1,r8,r9}
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@ Give read/write access to all the memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Sets MPU regions and cache settings
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adr r0, __abt_mpu_regions
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ldmia r0, {r1-r8}
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mov r0, #0b00110010 @ bootrom, arm9 mem and fcram are cacheable/bufferable
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mcr p15, 0, r1, c6, c0, 0
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mcr p15, 0, r2, c6, c1, 0
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mcr p15, 0, r3, c6, c2, 0
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mcr p15, 0, r4, c6, c3, 0
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mcr p15, 0, r5, c6, c4, 0
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mcr p15, 0, r6, c6, c5, 0
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mcr p15, 0, r7, c6, c6, 0
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mcr p15, 0, r8, c6, c7, 0
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enable mpu/caches
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ldr r1, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | CR_ENABLE_DTCM)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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ldr r2, =XRQ_DumpRegisters @ void XRQ_DumpRegisters(u32 xrq_id, u32 *regs)
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mov r1, sp
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mov r0, r11
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blx r2
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msr cpsr, #(SR_SVC_MODE | SR_IRQ | SR_FIQ)
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mov r0, #0
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.LXRQ_WFI:
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mcr p15, 0, r0, c7, c0, 4
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b .LXRQ_WFI
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.pool
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__abt_mpu_regions:
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.word 0x0000003F @ 00000000 4G | background region (includes IO regs)
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.word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected)
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.word 0x3000801B @ 30008000 16k | dtcm
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.word 0x00000035 @ 00000000 128M | itcm
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.word 0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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.word 0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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.word 0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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.word 0x1800002D @ 18000000 8M | vram (+ 2MB)
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.global XRQ_End
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XRQ_End:
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