mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 05:32:47 +00:00
2f86686388
- added initial SCU twiddling - added very untested and unusable SMP code - fixed race condition that happened on boot - added initial MMU code (just super basic identity mapping, no caching set up or anything) - enabled some of the fancier ARMv6 features - reorganized ARM11 files into their own folders - possibly more stuff I'm forgetting about
73 lines
1.2 KiB
ArmAsm
73 lines
1.2 KiB
ArmAsm
.section .text.boot
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.align 4
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#include <arm.h>
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#define STACK_SZ (8192)
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.global __boot
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__boot:
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cpsid aif, #SR_SVC_MODE
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@ Writeback and invalidate all DCache
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@ Invalidate all caches
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@ Data Synchronization Barrier
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 0
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mcr p15, 0, r0, c7, c7, 0
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mcr p15, 0, r0, c7, c10, 4
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@ Reset control registers
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ldr r0, =0x00054078
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ldr r1, =0x0000000F
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ldr r2, =0x00F00000
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r1, c1, c0, 1
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mcr p15, 0, r2, c1, c0, 2
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@ Get CPU ID
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mrc p15, 0, r12, c0, c0, 5
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ands r12, r12, #3
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@ Setup stack according to CPU ID
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ldr sp, =(_stack_base + STACK_SZ)
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ldr r0, =STACK_SZ
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mla sp, r0, r12, sp
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beq corezero_start
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cmp r12, #MAX_CPU
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blo coresmp_start
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1:
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wfi
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b 1b
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corezero_start:
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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.Lclearbss:
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cmp r0, r1
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strlt r2, [r0], #4
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blt .Lclearbss
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@ Set up IRQ vector
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ldr r0, =0x1FFFFFA0
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ldr r1, =0xE51FF004
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ldr r2, =irq_vector
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stmia r0, {r1, r2}
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coresmp_start:
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bl SYS_CoreInit
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bl MPCoreMain
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b __boot
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.section .bss.stack
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.align 3
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_stack_base:
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.space (MAX_CPU * STACK_SZ)
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