mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-25 21:22:47 +00:00
108 lines
3.0 KiB
ArmAsm
108 lines
3.0 KiB
ArmAsm
/*
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* This file is part of GodMode9
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* Copyright (C) 2017-2019 Wolfvak
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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.section .text.boot
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.align 4
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#include <arm.h>
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#define STACK_SZ (8192)
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.global __boot
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__boot:
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cpsid aif, #SR_SVC_MODE
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clrex
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@ Writeback and invalidate all DCache
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@ Invalidate all caches
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@ Data Synchronization Barrier
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 0
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mcr p15, 0, r0, c7, c7, 0
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mcr p15, 0, r0, c7, c10, 4
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@ Reset control registers
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ldr r0, =0x00054078
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ldr r1, =0x0000000F
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ldr r2, =0x00F00000
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r1, c1, c0, 1
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mcr p15, 0, r2, c1, c0, 2
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@ VFPv2 init
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@ https://github.com/derrekr/fastboot3DS/blob/f63c967369451b1fd0078e649cf0010fe10a62fd/source/arm11/start.s#L195
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mov r0, #0
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mov r1, #0xF00000 @ Give full access to cp10/11 in user and privileged mode
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mov r2, #0x40000000 @ Clear exception bits and enable VFP11
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mov r3, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode
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mcr p15, 0, r1, c1, c0, 2 @ Write Coprocessor Access Control Register
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mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer
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fmxr fpexc, r2 @ Write Floating-point exception register
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fmxr fpscr, r3 @ Write Floating-Point Status and Control Register
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@ Get CPU ID
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mrc p15, 0, r12, c0, c0, 5
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ands r12, r12, #3
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@ Setup stack according to CPU ID
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ldr sp, =(_stack_base + STACK_SZ)
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ldr r0, =STACK_SZ
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mla sp, r0, r12, sp
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beq corezero_start
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cmp r12, #MAX_CPU
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blo coresmp_start
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1:
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wfi
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b 1b
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corezero_start:
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@ assumes the .bss section size is 128 byte aligned (or zero)
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ldr r0, =__bss_pa
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ldr r1, =__bss_va_end @ calculate the length of .bss using the VA start and end
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ldr r2, =__bss_va
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sub r1, r1, r2
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add r1, r0, r1 @ fixup to be PA start and end
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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.Lclearbss:
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cmp r0, r1
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.rept (128 / 16) @ 16 bytes copied per block
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stmloia r0!, {r2-r5}
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.endr
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blo .Lclearbss
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bl SYS_CoreZeroInit
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coresmp_start:
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bl SYS_CoreInit
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ldr lr, =MainLoop
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bx lr
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.section .bss.stack
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.align 12 @ make sure stack is aligned to a page boundary
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.global _stack_base
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_stack_base:
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.space (MAX_CPU * STACK_SZ)
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