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https://github.com/d0k3/GodMode9.git
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137 lines
3.8 KiB
ArmAsm
137 lines
3.8 KiB
ArmAsm
.section .text.start
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.align 4
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.arm
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#include <arm.h>
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@ make sure not to clobber r0-r2
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.global _start
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_start:
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@ Switch to supervisor mode and disable interrupts
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msr cpsr_c, #(SR_SVC_MODE | SR_IRQ | SR_FIQ)
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@ Short delay (not always necessary, just in case)
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mov r3, #0x40000
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.Lwaitloop:
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subs r3, #1
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bgt .Lwaitloop
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@ Check the load address
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adr r3, _start
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ldr r4, =__start__
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cmp r3, r4
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beq _start_gm
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@ Relocate the binary to the correct location and branch to it
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ldr r5, =__code_size__
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.Lbincopyloop:
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subs r5, #4
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ldrge r6, [r3, r5]
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strge r6, [r4, r5]
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bge .Lbincopyloop
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mov r5, r0
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mov r6, r1
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mov r7, r2
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ldr r3, =0xFFFF0830 @ Writeback & Invalidate DCache
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blx r3
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mov r0, r5
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mov r1, r6
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mov r2, r7
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mov lr, #0
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mcr p15, 0, lr, c7, c5, 0 @ Invalidate ICache
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bx r4
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_start_gm:
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ldr sp, =__stack_top
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mov r9, r0 @ argc
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mov r10, r1 @ argv
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ldr r4, =0xBEEF
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lsl r2, #16
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lsr r2, #16
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cmp r2, r4 @ magic word
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movne r9, #0
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@ Disable caches / mpu
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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bic r4, #(1<<16) @ - dtcm disable (mandated by the docs, before you change the dtcm's address)
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bic r4, #(1<<12) @ - instruction cache disable
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bic r4, #(1<<2) @ - data cache disable
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bic r4, #(1<<0) @ - mpu disable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Clear bss
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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.Lbss_clr:
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cmp r0, r1
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strlt r2, [r0], #4
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blt .Lbss_clr
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@ Invalidate caches
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mov r5, #0
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mcr p15, 0, r5, c7, c5, 0 @ invalidate I-cache
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mcr p15, 0, r5, c7, c6, 0 @ invalidate D-cache
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mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
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@ Give read/write access to all the memory regions
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ldr r5, =0x33333333
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mcr p15, 0, r5, c5, c0, 2 @ write data access
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mcr p15, 0, r5, c5, c0, 3 @ write instruction access
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@ Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001F @ ffff0000 64k | bootrom (unprotected / protected)
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ldr r1, =0x3000801B @ 30008000 16k | dtcm
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ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r3, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r8, #0b00101101 @ bootrom/itcm/arm9 mem and fcram are cacheable/bufferable
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enable dctm
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ldr r1, =0x3000800A @ set dtcm
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mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
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@ Wait for screen init
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mov r0, #0x20000000
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.Lwaitforsi:
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ldr r1, [r0, #-4]
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cmp r1, #0
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bne .Lwaitforsi
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@ Enable caches
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<18) @ - itcm enable
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orr r4, r4, #(1<<16) @ - dtcm enable
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Fixes mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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mov r0, r9
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mov r1, r10
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b main
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