mirror of
https://github.com/d0k3/GodMode9.git
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101 lines
3.9 KiB
C
101 lines
3.9 KiB
C
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// Copyright 2014 Normmatt
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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//
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// modifyed by osilloscopion (2 Jul 2016)
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//
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#pragma once
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#include <inttypes.h>
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#include "delay.h"
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#define u8 uint8_t
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#define u16 uint16_t
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#define u32 uint32_t
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#define u64 uint64_t
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#define vu8 volatile u8
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#define vu16 volatile u16
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#define vu32 volatile u32
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#define vu64 volatile u64
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#define REG_ROMCTRL (*(vu32*)0x10164004)
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#define REG_AUXSPICNT (*(vu16*)0x10164000)
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#define REG_AUXSPICNTH (*(vu16*)0x10164001)
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#define REG_AUXSPIDATA (*(vu16*)0x10164002)
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#define CARD_COMMAND ((vu8*)0x10164008)
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#define CARD_DATA_RD (*(vu32*)0x1016401C)
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#define CARD_CR1_ENABLE 0x8000u
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#define CARD_CR1_IRQ 0x4000u
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// SPI EEPROM COMMANDS
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#define SPI_EEPROM_WRSR 0x01
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#define SPI_EEPROM_PP 0x02 // Page Program
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#define SPI_EEPROM_READ 0x03
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#define SPI_EEPROM_WRDI 0x04 // Write disable
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#define SPI_EEPROM_RDSR 0x05 // Read status register
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#define SPI_EEPROM_WREN 0x06 // Write enable
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#define SPI_EEPROM_PW 0x0a // Page Write
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#define SPI_EEPROM_FAST 0x0b // Fast Read
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#define SPI_EEPROM_RDID 0x9f
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#define SPI_EEPROM_RDP 0xab // Release from deep power down
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#define SPI_EEPROM_DPD 0xb9 // Deep power down
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#define CARD_ACTIVATE (1u<<31) // when writing, get the ball rolling
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#define CARD_WR (1u<<30) // Card write enable
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#define CARD_nRESET (1u<<29) // value on the /reset pin (1 = high out, not a reset state, 0 = low out = in reset)
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#define CARD_SEC_LARGE (1u<<28) // Use "other" secure area mode, which tranfers blocks of 0x1000 bytes at a time
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#define CARD_CLK_SLOW (1u<<27) // Transfer clock rate (0 = 6.7MHz, 1 = 4.2MHz)
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#define CARD_BLK_SIZE(n) (((n)&0x7u)<<24) // Transfer block size, (0 = None, 1..6 = (0x100 << n) bytes, 7 = 4 bytes)
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#define CARD_SEC_CMD (1u<<22) // The command transfer will be hardware encrypted (KEY2)
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#define CARD_DELAY2(n) (((n)&0x3Fu)<<16) // Transfer delay length part 2
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#define CARD_SEC_SEED (1u<<15) // Apply encryption (KEY2) seed to hardware registers
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#define CARD_SEC_EN (1u<<14) // Security enable
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#define CARD_SEC_DAT (1u<<13) // The data transfer will be hardware encrypted (KEY2)
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#define CARD_DELAY1(n) ((n)&0x1FFFu) // Transfer delay length part 1
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// 3 bits in b10..b8 indicate something
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// read bits
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#define CARD_BUSY (1u<<31) // when reading, still expecting incomming data?
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#define CARD_DATA_READY (1u<<23) // when reading, REG_NTRCARDFIFO has another word of data and is good to go
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// Card commands
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#define CARD_CMD_DUMMY 0x9Fu
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#define CARD_CMD_HEADER_READ 0x00u
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#define CARD_CMD_HEADER_CHIPID 0x90u
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#define CARD_CMD_ACTIVATE_BF 0x3Cu // Go into blowfish (KEY1) encryption mode
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#define CARD_CMD_ACTIVATE_BF2 0x3Du // Go into blowfish (KEY1) encryption mode
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#define CARD_CMD_ACTIVATE_SEC 0x40u // Go into hardware (KEY2) encryption mode
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#define CARD_CMD_SECURE_CHIPID 0x10u
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#define CARD_CMD_SECURE_READ 0x20u
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#define CARD_CMD_DISABLE_SEC 0x60u // Leave hardware (KEY2) encryption mode
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#define CARD_CMD_DATA_MODE 0xA0u
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#define CARD_CMD_DATA_READ 0xB7u
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#define CARD_CMD_DATA_CHIPID 0xB8u
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//REG_AUXSPICNT
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#define CARD_ENABLE (1<<15)
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#define CARD_SPI_ENABLE (1<<13)
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#define CARD_SPI_BUSY (1<<7)
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#define CARD_SPI_HOLD (1<<6)
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#define CARD_SPICNTH_ENABLE (1<<7) // in byte 1, i.e. 0x8000
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#define CARD_SPICNTH_IRQ (1<<6) // in byte 1, i.e. 0x4000
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#define swiDelay(n) ioDelay(n)
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#define DMA_SRC(n) (*(vu32*)(0x10002004 + (n * 0x1c)))
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#define DMA_DEST(n) (*(vu32*)(0x10002008 + (n * 0x1c)))
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#define DMA_CR(n) (*(vu32*)(0x1000201C + (n * 0x1c)))
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#define DMA_ENABLE (1u << 31)
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#define DMA_START_CARD (5u << 27)
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#define DMA_32_BIT (1u << 26)
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#define DMA_REPEAT (1u << 25)
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#define DMA_SRC_FIX (1u << 24)
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void cardReset();
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