Mirror/Luma3DS
1
0
Fork 0
mirror of https://github.com/LumaTeam/Luma3DS.git synced 2026-02-22 01:44:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

kext: even more perf improvements

Browse Source 
Turns out the undef handler path is quite hot, as only one thread per core can have VFP enabled at a time.
This commit is contained in:
TuxSH 2022-04-12 23:53:58 +01:00
parent 1e95344588
commit d957494d45
3 changed files with 12 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
k11_extension/Makefile
View File

@ -25,7 +25,8 @@ INCLUDES := include include/svc
#---------------------------------------------------------------------------------
# options for code generation
#---------------------------------------------------------------------------------
ARCH := -march=armv6k -mtune=mpcore -mfloat-abi=hard -mtp=soft
# -mgeneral-regs-only so that the C code is guaranteed not to use FPU regs
ARCH := -march=armv6k -mtune=mpcore -mfloat-abi=hard -mtp=soft -mgeneral-regs-only
DEFINES := -DARM11 -D_3DS
FALSEPOSITIVES := -Wno-array-bounds -Wno-stringop-overflow -Wno-stringop-overread

31
k11_extension/source/fatalExceptionHandlers.s
View File

@ -24,23 +24,6 @@
.fpu vfp
.macro TEST_IF_MODE_AND_ARM_INST_OR_JUMP lbl, mode
cpsid aif
mrs sp, spsr
tst sp, #0x20
bne \lbl
and sp, #0x1f @ get previous processor mode
cmp sp, #\mode
bne \lbl
sub sp, lr, #4
mcr p15, 0, sp, c7, c8, 0 @ VA to PA translation with privileged read permission check
mrc p15, 0, sp, c7, c4, 0 @ read PA register
tst sp, #1 @ failure bit
bne \lbl
.endm
.macro GEN_USUAL_HANDLER name, index, pos
\name\()Handler:
ldr sp, =exceptionStackTop
@ -180,14 +163,20 @@ _commonHandler:
.type FIQHandler, %function
GEN_USUAL_HANDLER FIQ, 0, 28
.align 5
.global undefinedInstructionHandler
.type undefinedInstructionHandler, %function
undefinedInstructionHandler:
TEST_IF_MODE_AND_ARM_INST_OR_JUMP _undefinedInstructionNormalHandler, 0x10
@ Most of the time, we're here to re-enable the FPU (over and over again)
mrs sp, spsr
@ We can assume bit4 is always set in SPSR. Test if if it's not thumb and if it's usermode
tst sp, #0x2F
bne _undefinedInstructionNormalHandler
ldr sp, [lr, #-4] @ test if it's an VFP instruction that was aborted
@ Test if it's an VFP instruction that was aborted
ldr sp, [lr, #-4]
lsl sp, #4
sub sp, #0xc0000000
sub sp, #0xC0000000
cmp sp, #0x30000000
bcs _undefinedInstructionNormalHandler
fmrx sp, fpexc
@ -212,8 +201,6 @@ undefinedInstructionHandler:
.global prefetchAbortHandler
.type prefetchAbortHandler, %function
prefetchAbortHandler:
TEST_IF_MODE_AND_ARM_INST_OR_JUMP _prefetchAbortNormalHandler, 0x13
ldr sp, =(Break + 3*4 + 4)
cmp lr, sp
bne _prefetchAbortNormalHandler

10
k11_extension/source/svcHandler.s
View File

@ -24,7 +24,7 @@
.text
.arm
.balign 4
.align 5
.global svcHandler
.type svcHandler, %function
@ -45,14 +45,6 @@ svcHandler:
ldr r8, =alteredSvcTable
ldr r8, [r8, r9,lsl#2]
/*@ sp = page end - 0x110
add r0, sp, #0x110 @ page end
bl svcHook
cpsid i
mov r8, r0
ldmfd sp, {r0-r7, r12, lr}
*/
cmp r8, #0
beq _fallback @ invalid svc, or svc 0xff (stop point)