- use recursive stage 1 page table (thanks @fincs for this idea)
- NULL now unmapped
- no identity mapping
- image + GICv2 now mapped at the same address for every platform
- tempbss mapped just after "real" bss, can now steal unused mem from
the latter
- no hardcoded VAs for other MMIO devices
- tegra: remove timers, use the generic timer instead
- set/way cache ops create losses of coherency, do not broadcast and are only meant to be used on boot, period.
Cache ops by VA are **the only way** to do data cache maintenance.
Fix a bug where the L2 cache was evicted by each core. It shouldn't have.
- Cleaning dcache to PoU and invalidating icache to PoU, by VA is sufficient for self-modifying code
- Since we operate within a single cluster and don't do DMA, we almost always operate within the inner shareability domain
(commit untested on real hw)
