Tomasz Moń 0534e36cf8 Set SDMMC controller to SDR104 as a workaround ...

According to Tegra X1 Series Processors Silicon Errata there is possible
misalignment of received data which results in a CRC error. The issue is
present only in SDR50 mode.

2018-05-27 17:43:25 +02:00

..

src

Set SDMMC controller to SDR104 as a workaround

2018-05-27 17:43:25 +02:00

linker.ld

Refactor fusee's makefile

2018-05-27 00:59:02 +02:00

linker.specs

Revamp all the Makefiles (thanks @fincs @WinterMute)

2018-05-19 01:07:27 +02:00

Makefile

Revamp all the Makefiles (thanks @fincs @WinterMute)

2018-05-19 01:07:27 +02:00