mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2026-03-01 05:04:39 +00:00
626f0ecb98
- use recursive stage 1 page table (thanks @fincs for this idea) - NULL now unmapped - no identity mapping - image + GICv2 now mapped at the same address for every platform - tempbss mapped just after "real" bss, can now steal unused mem from the latter - no hardcoded VAs for other MMIO devices - tegra: remove timers, use the generic timer instead
256 lines
7.9 KiB
C
256 lines
7.9 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "uart.h"
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#include "pinmux.h"
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#include "gpio.h"
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#include "car.h"
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#include "../../irq.h"
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#include "../../timer.h"
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static uintptr_t g_uartRegBase;
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static inline volatile tegra_uart_t *uartGetRegisters(UartDevice dev)
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{
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static const size_t offsets[] = { 0, 0x40, 0x200, 0x300, 0x400 };
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return (volatile tegra_uart_t *)(g_uartRegBase + offsets[dev]);
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}
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static inline void uartWaitCycles(u32 baud, u32 num)
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{
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timerWaitUsecs((num * 1000000 + 16 * baud - 1) / (16 * baud));
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}
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static inline void uartWaitSyms(u32 baud, u32 num)
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{
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timerWaitUsecs((num * 1000000 + baud - 1) / baud);
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}
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static void uartSetPinmuxConfig(UartDevice dev) {
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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switch (dev) {
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case UART_A:
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pinmux->uart1_tx = 0;
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pinmux->uart1_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart1_rts = 0;
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pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_B:
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pinmux->uart2_tx = 0;
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pinmux->uart2_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart2_rts = 0;
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pinmux->uart2_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_C:
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pinmux->uart3_tx = 0;
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pinmux->uart3_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart3_rts = 0;
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pinmux->uart3_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_D:
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pinmux->uart4_tx = 0;
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pinmux->uart4_rx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart4_rts = 0;
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pinmux->uart4_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_E:
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// Unused.
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break;
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default: break;
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}
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}
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static void uartReset(UartDevice dev)
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{
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static const CarDevice uartCarDevs[] = { CARDEVICE_UARTA, CARDEVICE_UARTB, CARDEVICE_UARTC, CARDEVICE_UARTD };
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if (dev == UART_B) {
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gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_SFIO);
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} else {
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gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
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}
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if (dev == UART_C) {
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gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_SFIO);
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} else {
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gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
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}
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uartSetPinmuxConfig(dev);
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clkrst_reboot(uartCarDevs[dev]);
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}
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// This function blocks until the UART device is in the desired state.
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static void uartWaitIdle(UartDevice dev, UartVendorStatus status)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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if (status & UART_VENDOR_STATE_TX_IDLE) {
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while (!(uart->lsr & UART_LSR_TMTY));
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}
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if (status & UART_VENDOR_STATE_RX_IDLE) {
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while (uart->lsr & UART_LSR_RDR);
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}
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}
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void uartSetRegisterBase(uintptr_t regBase)
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{
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g_uartRegBase = regBase;
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}
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void uartInit(UartDevice dev, u32 baud, u32 flags)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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bool inverted = (flags & BIT(0)) != 0;
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// Set pinmux, gpio, clock
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uartReset(dev);
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// Wait for idle state.
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uartWaitIdle(dev, UART_VENDOR_STATE_TX_IDLE);
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// Calculate baud rate, round to nearest.
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u32 rate = (8 * baud + 408000000) / (16 * baud);
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uart->lcr &= ~UART_LCR_DLAB; // Disable DLAB.
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uart->ier = 0; // Disable all interrupts.
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uart->mcr = 0;
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// Setup UART in FIFO mode
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uart->lcr = UART_LCR_DLAB | UART_LCR_WD_LENGTH_8; // Enable DLAB and set word length 8.
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uart->dll = (u8)rate; // Divisor latch LSB.
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uart->dlh = (u8)(rate >> 8); // Divisor latch MSB.
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uart->lcr &= ~UART_LCR_DLAB; // Disable DLAB.
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uart->spr; // Dummy read.
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uartWaitSyms(baud, 3); // Wait for 3 symbols at the new baudrate.
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// Enable FIFO with default settings.
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uart->fcr = UART_FCR_FCR_EN_FIFO;
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uart->irda_csr = inverted ? UART_IRDA_CSR_INVERT_TXD : 0; // Invert TX if needed
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uart->spr; // Dummy read as mandated by TRM.
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uartWaitCycles(baud, 3); // Wait for 3 baud cycles, as mandated by TRM (erratum).
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// Flush FIFO.
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uartWaitIdle(dev, UART_VENDOR_STATE_TX_IDLE); // Make sure there's no data being written in TX FIFO (TRM).
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uart->fcr |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; // Clear TX and RX FIFOs.
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uartWaitCycles(baud, 32); // Wait for 32 baud cycles (TRM, erratum).
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// Wait for idle state (TRM).
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uartWaitIdle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
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// Set scratch register to 0. We'll use it to backup write-only IER later
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uart->spr = 0;
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// Register the interrupt ID
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configureInterrupt(uartGetIrqId(dev), IRQ_PRIORITY_HOST, true);
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}
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void uartWriteData(UartDevice dev, const void *buffer, size_t size)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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const u8 *buf8 = (const u8 *)buffer;
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for (size_t i = 0; i < size; i++) {
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while (!(uart->lsr & UART_LSR_THRE)); // Wait until it's possible to send data.
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uart->thr = buf8[i];
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}
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}
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void uartReadData(UartDevice dev, void *buffer, size_t size)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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for (size_t i = 0; i < size; i++) {
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while (!(uart->lsr & UART_LSR_RDR)) // Wait until it's possible to receive data.
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buf8[i] = uart->rbr;
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}
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}
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size_t uartReadDataMax(UartDevice dev, void *buffer, size_t maxSize)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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size_t count = 0;
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for (size_t i = 0; i < maxSize && (uart->lsr & UART_LSR_RDR); i++) {
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buf8[i] = uart->rbr;
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++count;
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}
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return count;
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}
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size_t uartReadDataUntil(UartDevice dev, char *buffer, size_t maxSize, char delimiter)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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size_t count = 0;
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for (size_t i = 0; i < maxSize && (uart->lsr & UART_LSR_RDR); i++) {
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while (!(uart->lsr & UART_LSR_RDR)) // Wait until it's possible to receive data.
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buffer[i] = uart->rbr;
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++count;
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if (buffer[i] == delimiter) {
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break;
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}
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}
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return count;
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}
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ReadWriteDirection uartGetInterruptDirection(UartDevice dev)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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u32 ret = 0;
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u32 iir = uart->iir & 0xF;
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if (iir == 8 || iir == 12) {
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// Data ready or data timeout
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ret |= DIRECTION_READ;
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} else if (iir == 2) {
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// TX FIFO empty
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ret |= DIRECTION_WRITE;
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}
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return (ReadWriteDirection)ret;
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}
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void uartSetInterruptStatus(UartDevice dev, ReadWriteDirection direction, bool enable)
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{
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volatile tegra_uart_t *uart = uartGetRegisters(dev);
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u32 mask = 0;
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if (direction & DIRECTION_READ) {
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mask |= UART_IER_IE_RX_TIMEOUT | UART_IER_IE_RHR;
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}
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if (direction & DIRECTION_WRITE) {
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mask |= UART_IER_IE_THR;
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}
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if (enable) {
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uart->spr |= mask;
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uart->ier = uart->spr;
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} else {
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uart->spr &= ~mask;
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uart->ier = uart->spr;
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}
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}
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