mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2026-03-01 05:04:39 +00:00
291 lines
9.4 KiB
C++
291 lines
9.4 KiB
C++
/*
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* Copyright (c) 2019-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <mutex>
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#include "hvisor_irq_manager.hpp"
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#include "platform/interrupt_config.h"
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#include "core_ctx.h"
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#include "guest_timers.h"
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#include "transport_interface.h"
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#include "timer.h"
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#include "vgic.h"
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//#include "debug_manager.h"
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namespace {
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inline bool checkRescheduleEmulatedPtimer(ExceptionStackFrame *frame)
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{
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// Evaluate if the timer has really expired in the PoV of the guest kernel.
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// If not, reschedule (add missed time delta) it & exit early
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u64 cval = currentCoreCtx->emulPtimerCval;
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u64 vct = computeCntvct(frame);
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if (cval > vct) {
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// It has not: reschedule the timer
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// Note: this isn't 100% precise esp. on QEMU so it may take a few tries...
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writeEmulatedPhysicalCompareValue(frame, cval);
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return false;
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}
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return true;
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}
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inline bool checkGuestTimerInterrupts(ExceptionStackFrame *frame, u32 irqId)
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{
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// A thing that might have happened is losing the race vs disabling the guest interrupts
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// Another thing is that the virtual timer might have fired before us updating voff when executing a top half?
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if (irqId == TIMER_IRQID(NS_VIRT_TIMER)) {
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u64 cval = THERMOSPHERE_GET_SYSREG(cntp_cval_el0);
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return cval <= computeCntvct(frame);
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} else if (irqId == TIMER_IRQID(NS_PHYS_TIMER)) {
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return checkRescheduleEmulatedPtimer(frame);
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} else {
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return true;
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}
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}
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}
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namespace ams::hvisor {
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bool IrqManager::IsGuestInterrupt(u32 id)
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{
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// We don't care about the interrupts we don't use
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bool ret = true;
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ret = ret && id != GIC_IRQID_MAINTENANCE;
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ret = ret && id != GIC_IRQID_NS_PHYS_HYP_TIMER;
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ret = ret && transportInterfaceFindByIrqId(id) == NULL;
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return ret;
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}
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void IrqManager::InitializeGic()
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{
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// Reinits the GICD and GICC (for non-secure mode, obviously)
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if (currentCoreCtx->isBootCore && !currentCoreCtx->warmboot) {
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// Disable interrupt handling & global interrupt distribution
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gicd->ctlr = 0;
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// Get some info
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m_numSharedInterrupts = 32 * (gicd->typer & 0x1F); // number of interrupt lines / 32
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// unimplemented priority bits (lowest significant) are RAZ/WI
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gicd->ipriorityr[0] = 0xFF;
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m_priorityShift = 8 - __builtin_popcount(gicd->ipriorityr[0]);
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m_numPriorityLevels = static_cast<u8>(BIT(__builtin_popcount(gicd->ipriorityr[0])));
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m_numCpuInterfaces = static_cast<u8>(1 + ((gicd->typer >> 5) & 7));
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m_numListRegisters = static_cast<u8>(1 + (gich->vtr & 0x3F));
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}
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// Only one core will reset the GIC state for the shared peripheral interrupts
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u32 numInterrupts = 32;
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if (currentCoreCtx->isBootCore) {
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numInterrupts += m_numSharedInterrupts;
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}
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// Filter all interrupts
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gicc->pmr = 0;
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// Disable interrupt preemption
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gicc->bpr = 7;
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// Note: the GICD I...n regs are banked for private interrupts
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// Disable all interrupts, clear active status, clear pending status
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for (u32 i = 0; i < numInterrupts / 32; i++) {
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gicd->icenabler[i] = 0xFFFFFFFF;
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gicd->icactiver[i] = 0xFFFFFFFF;
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gicd->icpendr[i] = 0xFFFFFFFF;
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}
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// Set priorities to lowest
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for (u32 i = 0; i < numInterrupts; i++) {
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gicd->ipriorityr[i] = 0xFF;
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}
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// Reset icfgr, itargetsr for shared peripheral interrupts
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for (u32 i = 32 / 16; i < numInterrupts / 16; i++) {
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gicd->icfgr[i] = 0x55555555;
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}
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for (u32 i = 32; i < numInterrupts; i++) {
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gicd->itargetsr[i] = 0;
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}
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// Now, reenable interrupts
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// Enable the distributor
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if (currentCoreCtx->isBootCore) {
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gicd->ctlr = 1;
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}
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// Enable the CPU interface. Set EOIModeNS=1 (split prio drop & deactivate priority)
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gicc->ctlr = BIT(9) | 1;
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// Disable interrupt filtering
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gicc->pmr = 0xFF;
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}
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void IrqManager::DoConfigureInterrupt(u32 id, u8 prio, bool isLevelSensitive)
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{
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ClearInterruptEnabled(id);
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ClearInterruptPending(id);
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if (id >= 32) {
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SetInterruptMode(id, isLevelSensitive);
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DoSetInterruptAffinity(id, 0xFF); // all possible processors
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}
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SetInterruptShiftedPriority(id, prio << m_priorityShift);
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SetInterruptEnabled(id);
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}
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void IrqManager::Initialize()
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{
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u64 flags = MaskIrq();
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m_lock.lock();
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InitializeGic();
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for (u32 i = 0; i < MaxSgi; i++) {
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DoConfigureInterrupt(i, hostPriority, false);
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}
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DoConfigureInterrupt(GIC_IRQID_MAINTENANCE, hostPriority, true);
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vgicInit();
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m_lock.unlock();
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RestoreInterruptFlags(flags);
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}
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void IrqManager::ConfigureInterrupt(u32 id, u8 prio, bool isLevelSensitive)
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{
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u64 flags = MaskIrq();
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m_lock.lock();
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DoConfigureInterrupt(id, prio, isLevelSensitive);
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m_lock.unlock();
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RestoreInterruptFlags(flags);
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}
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void IrqManager::SetInterruptAffinity(u32 id, u8 affinity)
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{
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u64 flags = MaskIrq();
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m_lock.lock();
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DoSetInterruptAffinity(id, affinity);
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m_lock.unlock();
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RestoreInterruptFlags(flags);
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}
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void IrqManager::HandleInterrupt(ExceptionStackFrame *frame)
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{
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// TODO refactor c parts
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// Acknowledge the interrupt. Interrupt goes from pending to active.
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u32 iar = AcknowledgeIrq();
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u32 irqId = iar & 0x3FF;
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u32 srcCore = (iar >> 10) & 7;
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//DEBUG("EL2 [core %d]: Received irq %x\n", (int)currentCoreCtx->coreId, irqId);
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if (irqId == GicV2Distributor::spuriousIrqId) {
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// Spurious interrupt received
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return;
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} else if (!checkGuestTimerInterrupts(frame, irqId)) {
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// Deactivate the interrupt, return early
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DropCurrentInterruptPriority(iar);
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DeactivateCurrentInterrupt(iar);
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return;
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}
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bool isGuestInterrupt = false;
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bool isMaintenanceInterrupt = false;
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bool isPaused = false;
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bool hasDebugEvent = false;
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switch (irqId) {
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case ExecuteFunctionSgi:
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executeFunctionInterruptHandler(srcCore);
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break;
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case VgicUpdateSgi:
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// Nothing in particular to do here
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break;
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case DebugPauseSgi:
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// TODO debugManagerPauseSgiHandler();
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break;
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case ReportDebuggerBreakSgi:
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case DebuggerContinueSgi:
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// See bottom halves
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// Because exceptions (other debug events) are handling w/ interrupts off, if
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// we get there, there's no race condition possible with debugManagerReportEvent
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break;
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case GIC_IRQID_MAINTENANCE:
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isMaintenanceInterrupt = true;
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break;
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case TIMER_IRQID(CURRENT_TIMER):
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timerInterruptHandler();
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break;
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default:
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isGuestInterrupt = irqId >= 16;
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break;
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}
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TransportInterface *transportIface = irqId >= 32 ? transportInterfaceIrqHandlerTopHalf(irqId) : NULL;
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// Priority drop
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DropCurrentInterruptPriority(iar);
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isGuestInterrupt = isGuestInterrupt && transportIface == NULL && IsGuestInterrupt(irqId);
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instance.m_lock.lock();
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if (!isGuestInterrupt) {
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if (isMaintenanceInterrupt) {
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vgicMaintenanceInterruptHandler();
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}
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// Deactivate the interrupt
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DeactivateCurrentInterrupt(iar);
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} else {
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vgicEnqueuePhysicalIrq(irqId);
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}
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// Update vgic state
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vgicUpdateState();
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instance.m_lock.unlock();
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// TODO
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/*isPaused = debugManagerIsCorePaused(currentCoreCtx->coreId);
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hasDebugEvent = debugManagerHasDebugEvent(currentCoreCtx->coreId);
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if (irqId == ThermosphereSgi_ReportDebuggerBreak) DEBUG("debug event=%d\n", (int)debugManagerGetDebugEvent(currentCoreCtx->coreId)->type);
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// Bottom half part
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if (transportIface != NULL) {
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exceptionEnterInterruptibleHypervisorCode();
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unmaskIrq();
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transportInterfaceIrqHandlerBottomHalf(transportIface);
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} else if (irqId == ThermosphereSgi_ReportDebuggerBreak && !hasDebugEvent) {
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debugManagerReportEvent(DBGEVENT_DEBUGGER_BREAK);
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} else if (irqId == DebuggerContinueSgi && isPaused) {
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debugManagerUnpauseCores(BIT(currentCoreCtx->coreId));
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}*/
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}
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}
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